gerry@zds-ux.UUCP (Gerry Gleason) (02/24/90)
In article <AGLEW.90Feb21183552@oberon.csg.uiuc.edu> aglew@oberon.csg.uiuc.edu (Andy Glew) writes: >Now, let's see. Physical page addresses map to virtual? Via a hash >function? What ever happened to hash chaining? :-) Especially if the >TLB miss is handled in software (like on MIPS). IMHO this is one of the big wins in the MIPS design. Although I didn't know people used inverted page tables before this thread started, as you point out, this kind of hardware can efficiently support inverted page tables. It wouldn't surprise me if a MIPS processor could handle a TLB miss faster than an similar hardware implementation, and it certainly wouldn't be a performance hit. Soft page tables are also a good match for the MACH virtual memory system. One of my coworkers was told by a MACH person that the best hardware to run their memory system on is either completely stripped down like MIPS, or to directly implement their machine independent tables in the hardware (although this may loose due to the hit in MMU hardware complexity effecting the overall performance). One question, do inverted page tables really amount to a space for speed tradoff, or something else? Gerry Gleason