mccalpin@masig3.ocean.fsu.edu (John D. McCalpin) (11/17/89)
In article <31547@hal.mips.COM> mark@mips.COM (Mark G. Johnson) writes: >> >>CMOS is wonderful, but the ECL/GaAs/BiCMOS folks talk an awful good >>fight about how it's a different world on the other side of 50 MHz. >> >It's a terrible shame that CMOS parts are being shipped to customers, >for money, which operate over 50MHz. The ECL/GaAs/BiCMOS folks have >apparently discovered reasons why it can't be done. [... List of high-speed (> 50 MHz) devices deleted ...] Don't forget the ETA-10. We have 4 CMOS CPU's here at FSU running at 140 MHz.... I think that CDC is planning on using this technology in their recently announced Cyber 2000 "supermainframe". It may have failed in the market, but there is lots of pretty impressive hardware in the ETA-10.... -- John D. McCalpin - mccalpin@masig1.ocean.fsu.edu mccalpin@scri1.scri.fsu.edu mccalpin@delocn.udel.edu
mark@mips.COM (Mark G. Johnson) (11/17/89)
In article <7000@pt.cs.cmu.edu> lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay) writes: >... power demand that is also independent of the clock, that is, >absolutely constant rather than cyclic. > >CMOS isn't like that. It's asymmetric, and cares about transitions: >0= >1 takes more power than 1= >1. So, one can write worst-case >programs, which generate on-chip noise (mass transitions on the wide >datapath), or which generate board noise and heat (mass transitions >on the address and data pins). I'm not sure what cache activity >generally produces the most heat: it may depend on implementation. > >CMOS is wonderful, but the ECL/GaAs/BiCMOS folks talk an awful good >fight about how it's a different world on the other side of 50 MHz. > It's a terrible shame that CMOS parts are being shipped to customers, for money, which operate over 50MHz. The ECL/GaAs/BiCMOS folks have apparently discovered reasons why it can't be done. Perhaps Brooktree ought to initiate a recall of their CMOS devices "Bt458" and "Bt468", which operate at 170 and 200 MHz respectively. Performance Semiconductor and Cypress Semiconductor had better quit sending 125MHz full-CMOS static RAMs (P4C122, 7C123) to customers, and their datasheets for 200MHz CMOS parts (P3C3147) might need to be stamped "proven impossible" quickly. Even more alarming, the Japanese are in on this conspiracy :-) of faster-than-is-possible CMOS, too. Toshiba dares to offer, at 67MHz, their TC5588 CMOS RAM. The video DRAM from Japan's NMB Semiconductor is suspiciously too-fast as well. -- -- Mark Johnson MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086 (408) 991-0208 mark@mips.com {or ...!decwrl!mips!mark}
slackey@bbn.com (Stan Lackey) (11/18/89)
In article <31547@hal.mips.COM> mark@mips.COM (Mark G. Johnson) writes: >In article <7000@pt.cs.cmu.edu> lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay) writes: > >CMOS isn't like that. It's asymmetric, and cares about transitions: > >0= >1 takes more power than 1= >1. So, one can write worst-case > >programs, which generate on-chip noise (mass transitions on the wide > >datapath), or which generate board noise and heat (mass transitions > >on the address and data pins). I'm not sure what cache activity > >generally produces the most heat: it may depend on implementation. >It's a terrible shame that CMOS parts are being shipped to customers, >for money, which operate over 50MHz. The ECL/GaAs/BiCMOS folks have >apparently discovered reasons why it can't be done. >Perhaps Brooktree ought to initiate a recall of their CMOS devices >"Bt458" and "Bt468", which operate at 170 and 200 MHz respectively. > etc etc The article didn't say "CMOS faster than 50MHz can't be done." The issue is not designing chips. The issue is putting them in a system and trying to get them to work. Just a few of the many system problems CMOS has that ECL doesn't have: The fast CMOS has such fast rise times that we EE's need to become physicists in order to design transmission lines good enough to maintian signal integrity, without slowing signals down so much you might as well use TTL. The fast CMOS has such fast rise times that ground bounce causes chips to malfunction. The fast CMOS often does not have enough DC drive to allow proper line termination. I'm not saying it can't be done; but it isn't for the faint of heart, let me tell you. The CMOS guys have a ways to go before they catch up to where the ECL guys are, in designing for highly reliable, high speed, system level interconnectivity. -Stan
lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay) (11/19/89)
In article <48393@bbn.COM> slackey@BBN.COM (Stan Lackey) writes: >The CMOS guys have a ways to go before they catch up to where the ECL >guys are, in designing for highly reliable, high speed, system level >interconnectivity. Obviously, high-end ECL systems have workable answers: they're pretty reliable. How about the new ECL from BIT, namely their SPARC and MIPS R6000? I haven't seen details yet, but I assume that there weren't enough pins to use a complementary pair for each IO. And when do we see a BiCMOS micro, with a CMOS core and ECL IO? Or will the core go BiCMOS too, to avoid all the di/dt issues that the ECL people are so quick to point out? -- Don D.C.Lindsay Carnegie Mellon Computer Science
hui@joplin.mpr.ca (Michael Hui) (11/19/89)
Isn't it true that 50 ohm transmission line drivers and receivers can be reliably and economically made in CMOS? I have seen quite a few papers in the IEEE Journal of Solid State Circuits outlining how to do just that. Once you have a controlled impedence transmission line on your PC board, _any_ data rate is possible provided the internal data rates of your chips are fast enough, and your line drivers and receivers are up to it.
bls@cs.purdue.EDU (Brian L. Stuart) (11/20/89)
In article <1906@eric.mpr.ca> hui@mprgate.mpr.ca writes: > >Isn't it true that 50 ohm transmission line drivers and receivers can be >reliably and economically made in CMOS? >Once you have a controlled impedence transmission line on your PC >board, _any_ data rate is possible provided the internal data rates of >your chips are fast enough, and your line drivers and receivers are up >to it. While transmission rates can be increased by using matched drivers and receivers, you also need to have the characteristic impedance of the intervening transmission line also matched. Things can get really weird if you have some fan-out (i.e. one driver and several receivers in parallel). Another drawback is that such drivers draw more current. In general, the idea is altogether feasable, but related factors are one of the reasons that design of machines like Cray's is difficult. Brian L. Stuart Department of Computer Science Purdue University
weaver@weitek.WEITEK.COM (11/21/89)
In article <7032@pt.cs.cmu.edu> lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay) writes: >In article <48393@bbn.COM> slackey@BBN.COM (Stan Lackey) writes: >.... >And when do we see a BiCMOS micro, with a CMOS core and ECL IO? Or >will the core go BiCMOS too, to avoid all the di/dt issues that the >ECL people are so quick to point out? >-- >Don D.C.Lindsay Carnegie Mellon Computer Science BiCMOS implementations look good for the next generation of micros. These parts may be a bit slower than all ECL, but lower power, and a bit denser. I expect that they will look attractive for mid-line workstations, with ECL, GaAs, and liquid cooled chips possibilities for the high-end. BiCMOS is a process that allows bipolar transistors and MOS transistors on the same die. The bipolar transistors are not particularly faster than the CMOS, since they are made of the same silicon. I see four advantages to ECL over CMOS in this case: 1. low voltage swing (for faster transitions). 2. constant current (noise through power lines minimized). 3. smooth rise / fall (less noise generation). 4. high output current. And two disadvantages: 5. bigger. 6. higher power. For a chip with ECL IO and CMOS core, most of the power will be going to the output pin drivers. So advantage #2 is unimportant for the core. Internal wires on a chip are very resistive-capacitive, and require little current. So advantages #3 & #4 are not important for the core. That leaves advantage #1, which hardly seems worth the increase in power and size. Unless, of course, you really want to pay for speed. But then you would be better off with the best bipolar transistors that money can buy, and forget about BiCMOS. Michael Weaver.
toms@omews44.intel.com (Tom Shott) (11/28/89)
Another advantage to BiCMOS over those listed is: 5. Schottky clamp diodes (reduced ringing). I have heard system designers say they would sell their soul for a process that would just allow Schottky clamp diodes. You can design a CMOS driver w/ a low voltage swing, controlled edge rates and fairly high drive (not as high as BiCMOS but..). No question it burns area, but then area is cheap (cheaper then a new process, any body know how many more steps a BiCMOS process has over a CMOS process ? Steps cost money and reduce yield). -- ----------------------------------------------------------------------------- Tom Shott INTeL, 2111 NE 25th Ave., Hillsboro, OR 97123, (503) 696-4520 toms@omews44.intel.com OR toms%omews44.intel.com@csnet.relay.com INTeL.. Designers of the 960 Superscalar uP and other uP's