earl@mips.COM (Earl Killian) (05/24/88)
Several weeks ago I posted a proposed form for describing architectures and their implementations. I got some feedback, which I generally incorporated. The goal is to provide a uniform way to describe new products. Now it's finally time to give some examples. Two will follow. One for the MIPS R3000, and one for the Motorola 88000. I welcome other submissions, as well as corrections. First the updated blank form. Some definitions of my terminology are in order, because it's probably different from everyone else's. The latency of an operation is the time it takes for the entire operation to complete. The issue time is the time before you can start the next instruction, and the repeat time is the time until you can start another instruction of the same type. For example, a machine might require 3 cycles for a load instruction: 1 to calculate the address, 2 to access the cache, and allow a new load every 2 cycles, but allow a non-load to start immediately. I describe this load as 3/1/2. What is commonly called the load delay (as opposed to latency) is the time after the load before you can reference the result. This is the latency minus the issue time (3 - 1 = 2) in this case. Don't confuse latency with delay. Some latency/issue/repeat examples from the Cray-1S (from memory, so don't quote me): logicals: 1/1/1 shift: 2/1/1 integer add: 3/1/1 load: 11/2/2 I.e. most instructions are fully pipelined, but loads take two cycles before you can consider another instruction. An example of a multi-cycle latency, non-pipelined floating point unit might have: add: 2/1/2 mul: 4/1/4 A non-pipelined machine would generally have issue = latency, giving something like add: 2/2/2 I hope that is clear enough. If not, I'll try to clarify. "n.a." = not applicable "???" = don't know > Architecture Reference Where is the architecture fully described? > Peak native MIPS What is the clock cycle time? What is the peak native MIPS rate? > Implementation technology What are the parameters of the implementation technology? How many chips of what kinds to build a typical cpu subsystem? How many pins on those chips? > Instruction format What instruction sizes are used? What size are immediate operands? What size are branch displacements? > Integer Registers How are the registers organized [simple, windowed]? How many total integer registers? Hardwired zero register? For windowed machines: How many registers are addressed by an instruction? How many of these are not windowed? What window increments are supported? Window overflow and underflow are handled in [software, hardware]? > Integer Alu What is the logical latency/issue/repeat? What is the shift latency/issue/repeat? What is the add latency/issue/repeat? What is the compare latency/issue/repeat? How is 64 bit (signed/unsigned) integer addition supported and how many cycles? How are 64 bit (signed/unsigned) integer comparisons supported? > Branches Which operand comparisons are implemented in the conditional branch instruction, and which require a separate instruction? Where is the result of separate comparisons stored [registers, condition codes]? Which forms of branch delay are present in instruction set [execute N if no branch, execute N if branch, execute N always]? What are the taken and not-taken cycle counts for each branch type? > Loads/Stores What addressing mode(s) do load instructions use? What addressing mode(s) do store instructions use? Which load/store sizes are supported [8, 16, 32, 64]? What is the load latency/issue/repeat? What is the store latency/issue/repeat? > Integer Multiply/Divide How is multiply is implemented [software, multiply step, hardware]? How many cycles to perform 32x32->32 multiply? How is divide is implemented [software, divide step, hardware]? How many cycles to perform 32x32->32 divide? How is 32x32->64 bit integer multiplication supported and how many cycles? How is 64/32->32,32 bit integer division supported and how many cycles? > Floating Point Are floating point registers separate from integer registers? How many 32-bit floating point registers? How many 64-bit floating point registers? How many 80-bit floating point registers? How is floating point is implemented [software, coprocessor, on-chip]? What are the floating point operation latency/issue/repeats? 32-bit 64-bit 80-bit add mul div sqrt Which floating point units can operate in parallel? Can floating point operate in parallel with integer? Are floating point exceptions precise? > Memory management Page size in bytes? How many bits in a virtual address? What is the size of the user-mode address space? How many bits in a physical address? How many bits of address space id are added to virtual addresses, if any? Translation cache [none, off-chip, on-chip]? Translation cache size in entries? Translation cache associativity [direct-mapped, 2-set, 4-set, full]? Translation cache miss handled by [software, hardware]? > Caches Instruction cache [none, off-chip, on-chip]? Data cache [none, off-chip, on-chip]? Are I and D caches separate? I-cache total size in bytes? I-cache associativity [direct-mapped, 2-set, 4-set, fully associative]? I-cache address block size in bytes (bytes per tag)? I-cache transfer block size in bytes (bytes read on cache miss)? I-cache index [virtual, physical]? I-cache tag [virtual, physical]? D-cache total size in bytes? D-cache associativity [direct-mapped, 2-set, 4-set, fully associative]? D-cache writes [write-through, write-back]? D-cache address block size in bytes (bytes per tag)? D-cache transfer block size in bytes (bytes read on cache miss)? D-cache index [virtual, physical]? D-cache tag [virtual, physical]? Is there a secondary cache? If so, describe. > Branch Prediction What form of branch prediction is used, if any? > Other Describe other unique or interesting features of the architecture or its implementation. E.g. describe the functional units, with emphasis on non-standard units. -- UUCP: {ames,decwrl,prls,pyramid}!mips!earl USPS: MIPS Computer Systems, 930 Arques Ave, Sunnyvale CA, 94086