loving@lanai.cs.ucla.edu (10/19/88)
I don't care who wrote it, but this was posted: >Transmission line effects on a chip? Just how big *are* your chips >anyway? The only reason that transmission line effects are not serious is because RC delays dominate. The speed of light is 29.979 cm/nsec; RC delays down busses on chips (1u lines, 1mm long, .01 ohm/sq, .03fF/sq u) are on the order of 0.3 to 1.0 nano seconds. This does not take into account the time to charge the gate capacitance of the transistor(s) at the other end of this 1000u long line. Now if we used transmission lines instead of 'RC delay lines' the time to drive the signal down the line would be somewhere on the order of c/2 (speed of light) or more like 1 pico second. 1 nano second is pretty killer on a 10 or 15 nsec chip. 1 picosecond would not be. Mike Loving loving@lanai.cs.ucla.edu
stevew@nsc.nsc.com (Steve Wilson) (10/20/88)
In article <16939@shemp.CS.UCLA.EDU> loving@CS.UCLA.EDU () writes: >I don't care who wrote it, but this was posted: > >>Transmission line effects on a chip? Just how big *are* your chips >>anyway? > >The only reason that transmission line effects are not serious is because >RC delays dominate. The speed of light is 29.979 cm/nsec; RC delays down >busses on chips (1u lines, 1mm long, .01 ohm/sq, .03fF/sq u) are on the order >of 0.3 to 1.0 nano seconds. This does not take into account the time to >charge the gate capacitance of the transistor(s) at the other end of this >1000u long line. Now if we used transmission lines instead of 'RC delay >lines' the time to drive the signal down the line would be somewhere on >the order of c/2 (speed of light) or more like 1 pico second. 1 nano >second is pretty killer on a 10 or 15 nsec chip. 1 picosecond would not >be. I've done lotsa work with ECL, and a bit with ECL gate-arrays. If I recall correctly, you have to pull signals internal to a ECL gate-array down with a terminating resistor just like you have to externally. I didn't do any of the timing analysis for the gate-arrays on the project I was on, but I do seem to recall that the major timing problems was capacitive loading. Some of the faster gate-array families had better drive capabilities for a given length of metal. This seemed to dominate the real performance of the array. In summary, are you guys sure your not confusing the requirment for a pull down resistor for having to deal with transmission lines? Steve Wilson National Semiconductor [The above is my opinion, not those of my employer.]