jkenton@pinocchio.encore.com (Jeff Kenton) (02/13/90)
In article <1990Feb12.133414.1661@oracle.com> csimmons@oracle.com writes: >Now that FPUs and ALUs are being implemented on the same chip, maybe >it would make sense to implement a single register set instead of >two separate register sets. It would probably simplify certain aspects >of register allocation in compilers. Of course, the 88K seems to have >kept two separate register sets... > >-- Chuck The 88100 only has one set of registers (using pairs for double precision floating point). Rumor has it that the 88110 will have a separate set of 80-bit FP registers (as well as lots of other goodies).
mash@mips.COM (John Mashey) (02/13/90)
In article <11121@encore.Encore.COM> jkenton@pinocchio.encore.com (Jeff Kenton) writes: >In article <1990Feb12.133414.1661@oracle.com> csimmons@oracle.com writes: >>Now that FPUs and ALUs are being implemented on the same chip, maybe >>it would make sense to implement a single register set instead of >>two separate register sets. It would probably simplify certain aspects >>of register allocation in compilers. Of course, the 88K seems to have >>kept two separate register sets... >> >>-- Chuck > > >The 88100 only has one set of registers (using pairs for double precision >floating point). Rumor has it that the 88110 will have a separate set of >80-bit FP registers (as well as lots of other goodies). As has been discussed earlier, although having a single set of registers may simplify some things (it does), it also makes other things more complex: a) FP registers are naturally 64-bit things. b) Typically, current RISCs have 2 read + 1 write port 32-bit integer register files. (there are variations of course, but thisworks well with most of the current 3-operand integer pipelines). c) FP register files often want more ports, especially given that the inherently multi-cycle operations need to do writes, and you get stalls if there aren't enough ports. The more parallel units you have, the more ports you're likely to need, or else, you go to relabeling schemes, or else you get more stalls. Hence, there is a reason that most machines have separate integer and FP registers: it's an easy way to get more cheap register ports, leave the integer datapath 32-bits wide, and have the FP one 64-bits wide. d) Now, think about what happens if you go with one of the superscalar pipelines: you've just upped the number of register references that need to be satisifed by at least 2 (for 2-way superscalar), or more (for more). Of course, appropriate statistical analysis may help you make the right tradeoffs, because this could start to get expensive, and if you do something fancy in one part of the pipeline, and don't improve the access to machine resources in a well-balanced fashion, you're not going to gain as much as you thought. Anyway, if they really are putting a separate set of registers, it will certainly be a good thing for them. -- -john mashey DISCLAIMER: <generic disclaimer, I speak for me only, etc> UUCP: {ames,decwrl,prls,pyramid}!mips!mash OR mash@mips.com DDD: 408-991-0253 or 408-720-1700, x253 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086
wallwey@boulder.Colorado.EDU (WALLWEY DEAN WILLIAM) (02/13/90)
If I remmember right, the i860 already has 64 bit registers. Can anybody confirm or deny this. If so, are these the general registers or only floating point ones. Also I think I remmember the designers used 128 bit busses on the chip to keep certain parts of it from starving. Even if the i860 is not in any way a 64 bit proccessor, I really think you will see 64 bit busses in 1-2 years. I also think it would be very limiting to make the address bus size less than your data bus. Granted, you don't need it right now, but that is what they said about 16bit, and 32 bit busses when they first came out. Many of today's memmory systems already have 64 bit wide data paths to help with the memory bottle-neck problems. Of course using just 128 pins for the data and address bus could be a problem, but for a long time breaking the 40 pin barrier was thought to be to expensive for commodity systems. There will obviously be some advantages:Even if the instruction size stays at 32 bits or less, you can grab 2 instructions in the same clock cycle leaving alternate memory cycles for data reads and writes. Another advatage for floating point intensive applications is the ability to read and write double floats in a single memory cycle. Seeing these advatges, you might even see a 64bit 80786 or 68070. (Just a guess.) Write back, or post--I'm always interested in what people think. ---Dean
ccplumb@lion.waterloo.edu (Colin Plumb) (02/13/90)
In article <16886@boulder.Colorado.EDU> wallwey@boulder.Colorado.EDU (WALLWEY DEAN WILLIAM) writes: > If I remmember right, the i860 already has 64 bit registers. >Can anybody confirm or deny this? If so, are these the general >registers or only floating point ones. Also I think I remember >the designers used 128 bit busses on the chip to keep certain parts of >it from starving. When I posted my i860 summary, I said that it could lay claim to being the first 64-bit microprocessor. It has a 64-bit external bus, and a fair number of 64-bit operations. It still has 32-bit addresses and 32-bit integer registers, but the floating point unit and the (to my mind, very wierd) graphics units are 64 bits internally. Yes, it's far from pure, but all firsts are bastards in some way. The position is defnesible. -- -Colin