chips@usfvax2.UUCP (Chip Salzenberg) (07/24/87)
(This is in comp.arch now instead of comp.lang.c) In article <7098@alice.UUCP>, ark@alice.UUCP writes: > In article <398@sugar.UUCP>, peter@sugar.UUCP writes: > > I challenge anyone to come up with a faster interpreter anywhere (how can > > you beat one instruction?). This is actually what the threaded interpreter > > for the threaded version of DEC fortran-IV used, with R4==IP. > > How about zero instructions? > > At the end of each subroutine, instead of a return instruction, you just say > > jmp *(IP)+ > > That is, jump to the location addressed by the contents of the > word addressed by the contents of IP, and bump IP by one word. Yes, this is equivalent to the 6809's "JMP [,Y++]" instruction. I was severely disappointed by the 68000 architecture's lack of memory indirection. The 6809 remains the most elegant architecture for Forth [except for the Novix :-)], what with two stacks, indirect addressing, etc. (Donning asbestos suit for postnews line counter) -- Chip Salzenberg UUCP: "uunet!ateng!chip" or "chips@usfvax2.UUCP" A.T. Engineering, Tampa Fidonet: 137/42 CIS: 73717,366 "Use the Source, Luke!" My opinions do not necessarily agree with anything.
john@caeco.UUCP (John Rigby) (07/28/87)
in article <798@usfvax2.UUCP>, chips@usfvax2.UUCP (Chip Salzenberg) says: >> >> jmp *(IP)+ >> >> That is, jump to the location addressed by the contents of the >> word addressed by the contents of IP, and bump IP by one word. > > Yes, this is equivalent to the 6809's "JMP [,Y++]" instruction. I was > severely disappointed by the 68000 architecture's lack of memory indirection. How about this: rts Or in other words memory indirect through sp with post increment. Of course you can't do jsr's or handle interrupts on the same stack. John Rigby Caeco Inc. utah-cs!caeco!john