wittaya@uiucdcsm.cs.uiuc.edu (11/26/87)
I am wondering if anybody could help me with the following Pyramid 90X questions : 1. How are the multiple register sets managed? To be specific, they are used to keep some top control stack frames, 16 frames I presumed, and those below the current frame are addressed by virtual addresses. So when are they moved to the main storage? And how many frames are moved at a time? Do they work like a stack cache? I suspect that this is done by microprogram; i.e. whenever a call or a return executed, it checks for register overflow or underflow. Does this feature still exist in the later models? 2. Execution time, in term of number of cycles, for the instruction set as well as detail of the processor; e.g. how it is pipelined. I need the information for doing simulation of the machine. The processor architecture manual does not help me much. I would appreciate any suggestion. wittaya watchara (ihnp4!uiucdcs!wittaya or wittaya@m.cs.uiuc.edu) 1304 W. Springfiled Ave., Urbana, IL 61801