rtrauben@cortex.Eng.Sun.COM (Richard Trauben) (01/23/91)
lindsay@gandalf.cs.cmu.edu (Donald Lindsay) writes: >"...a five entry pending store queue and a four-entry store data >queue in the FPU enable the FXU [integer unit] to execute floating- >point store operations before the FPU produces the data. This allows >the FXU to generate the address, initiate TLB or cache reload >sequences, and check for data protection for a floating-point store >instruction, and then continue executing the subsequent instructions >without being held back by the FPU." If the address of a pending STF resides in the FPU result queue but the data is still unresolved, will any attempt be made to keep the entry cache coherent when a snoop hits on the address in question? -rich