chris@mimsy.umd.edu (Chris Torek) (01/03/90)
In article <34043@mips.mips.COM> mash@mips.COM (John Mashey) writes: >It is good to avoid over-generalizing: > a) Many RISCs do not have as many registers, i.e. in approximate > numbers of 32-bit registers, ignoring system registers: > 88K: 32 > MIPS & HP PA: 64 Also, at least on the MIPS Rx000s, half of those registers are in the FPU (the Rx010), and it is easy to tell whether a process is using the FPU, so (depending on job mix) the number of registers moved by a context switch may be 32 instead of 64. (Note that moving 32 registers implies 32 stores and 32 loads.) Of course, the MIPS reserves 2 of the integer registers to the kernel, so it is actually either 30 registers or 62 registers. . . . (Well, John did say `approximate' :-) ) -- In-Real-Life: Chris Torek, Univ of MD Comp Sci Dept (+1 301 454 7163) Domain: chris@cs.umd.edu Path: uunet!mimsy!chris
rogerk@mips.COM (Roger B.A. Klorese) (01/04/90)
In article <21600@mimsy.umd.edu> chris@mimsy.umd.edu (Chris Torek) writes: >Of course, the MIPS reserves 2 of the integer >registers to the kernel, so it is actually either 30 registers or 62 >registers. . . . > >(Well, John did say `approximate' :-) ) And, of course, R0==0 (hardwired), so that's 29 or 61... I'm pretty sure we don't save and restore 0 every time... ;-) -- ROGER B.A. KLORESE MIPS Computer Systems, Inc. phone: +1 408 720-2939 928 E. Arques Ave. Sunnyvale, CA 94086 rogerk@mips.COM {ames,decwrl,pyramid}!mips!rogerk "Two guys, one cart, fresh pasta... *you* figure it out." -- Suzanne Sugarbaker