mark@mips.COM (Mark G. Johnson) (10/26/88)
In article <28200216@urbsdc> aglew@urbsdc.Urbana.Gould.COM writes: > >As I understand it, there are two components of CMOS dynamic power >consumption: (1) the inherent power consumption as you go through >charge/discharge cycles on your nodes; (2) the transient that occurs >if both the n and p networks are switched on at the same, brief, >time, in transition. > >The first seems to be inherent. Cannot the second be controlled... (2) Sure. A standard stunt is to design a CMOS device such that abs(VTP) + abs(VTN) > abs(VDD) (in words, the turn-on voltages of the transistors are made large enough that it is impossible for them to be simultaneously on (with a fixed power supply)). This trick is common in low-power applications like telecom chips, calculators, and wristwatches. (1) Great strides in this area have been made in CMOS static RAM design --- presently the truly fast ones operate at 70-100 MHz. They just use good ole engineering to attack the supply-current equation I_ = n * C * (delta-V) / (delta-T) where n is the number of nodes switching; C is the average capacitance per node; delta-V is the voltage difference applied to the average capacitor; delta-T is the average duration of a charge/discharge cycle; and I_ is the long-term average (filtered over, say, 10**-1 seconds) dynamic current. -- -- Mark Johnson MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086 ...!decwrl!mips!mark (408) 991-0208