u5@mit-eddie.UUCP (03/27/87)
Enclosed please find a summery of the messages I received in response
to my question regarding memory management systems for small computer
systems. Thank you to all who responded.
-u5
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From: seismo!ihnp4!drutx!qwerty
Subject: Re: Memory Management on microcomputers
In-Reply-To: your article <4970@mit-eddie.MIT.EDU>
Try the pdp/8 series computers for interesting memory management.
A 12 bit address space machine that could handle 32K of memory. Once they
introduced bank switching, the memory space expanded to 128K. The memory
was 12 bits wide, and there were three bit reserved for the opcode (talk
about RISC), 1 bit for a zero page/current page address, and 7 bits of address
info (each page was 128 words). Instruction set: TAD (add to accumulator),
ISZ (increment memory and skip on zero), JSB (jump subroutine - stores return
address at the first location of the subroutine - makes recursive calls
interesting :-)), JMP, DCA (deposit and clear accumulator), IOT (input/output
transfer), AND (logical and to accumulator - makes OR and XOR interesting),
OPR - Operate group instructions - accumulator manipulation. Bank switching
instructions were relegated to reserved areas under the IOT group. Any given
instruction could reference 128 zero page words and 128 current page words
directly. It could reference 4096 words indirectly via the 256 current words.
It could reference all 32K with context switching prior to the indirect
instruction.
The small memory (typically 4 or 8 K on early machines) led to some neat coding.
Most I/O drivers fit in 128 words. The disk driver took 256. If you needed
a constant value, you first checked the assembled code on the current page
to see if one of the instructions happened to satisfy the value, before you
used another word for it. The second technique for generating constants was
to use the operate group. Clear AC, Comp AC, Shift Left AC was a quick way to
get -2. There were about 30 constants that could be generated this way.
Ah, the memories.
Brian Jones aka {ihnp4,}!{drutx,druhi}!qwerty @ AT&T-IS, Denver
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From: rajiv@im4u.utexas.edu (Rajiv N. Patel)
Subject: Reference for memory management..
Hi, I read your message on comp.arch and was reading an article regarding
Memory management on Microprocessors which may be of help to you.Here is
the reference:
"A Survey of Microprocessor Architectures for Memory Management",IEEE Computer
magazine,MARCH 1987, pp 48-67. (latest issue,came out a week back)
I do not know how much this article may help, but surely its a good place to
start.
Have a nice time donig your report.If possible I would appreciate to read the
completed report.
Rajiv Patel.
Dept of Electrical Eng.,U T Austin.
ARPA:rajiv@im4u.utexas.edu
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From: uwvax!uwmacc!uwmcsd1!grc!gary@harvard.harvard.edu
Apparently-To: uwmacc!uwvax!husc6!mit-eddie!u5
John DeRoo
MIT EE/CS Computer Facilites
RE: Memory Management on microcomputers
John:
I have done a lot of work with the National Semiconductor 32000
32 bit microprocessor family. (My company builds UNIX systems based
on the chip set). Try to get a copy of the 1986 Series 32000 Databook
from National. The first chapter details some of the reasons for the
32000 architecture especially why they use a Demand
Paged Virtual Memory Managment scheme (verses segmented, etc).
Some of the info is of course marketing hype, but you should find some
of it useful. Good luck on your paper.
Gary Sutcliffe (standard disclaimer ...)
General Robotics Corp. 23 S. Main St. Hartford, Wis. 53027
{allegra, ihnp4, seismo, harvard}uwvax!uwmacc!uwmcsd1!grc!gary