leech@rudolph.cs.unc.edu (07/17/90)
The i860 based custom graphics multicomputer we're developing,
Pixel-Planes, has a memory-mapped message transmit interface between
860 nodes: the transmit hardware snoops on the 860 address bus, and
sends words read from specific areas of memory. The mechanism for
sending a message, then, is to toggle the address bit reserved to the
transmit hardware and read the message one word at a time. To send
the right data, we must ensure that the message is in main memory, not
the cache. We are trying to accomplish this by flushing the cache
lines which might contain the message buffer before sending it. This
is where the problem lies: the i860 programmer's reference manual
says,
"The addresses used by the flush instruction refer to a reserved
4Kbyte memory area that is not used to store data. This ensures
that, when flushing the cache before a task switch, cached data
items from the old task are not transferred to the new task.
These addresses must be valid and writable in both the old and the
new task's space. Any other usage of flush has undefined
results."
Since we are running a single process in supervisor mode, the
caution about task switches should not apply. What we do is use the
address of the data buffer to be sent in the flush instruction, and
only flush a number of cache blocks corresponding to the message
length. This approach seems to contain a fatal error, but we've been
unable to characterize the problem, since our diagnostics rely on
being able to successfully send messages back to the host machine -
and the problem is in the message sending code. Attempts to use the
i860 simulator supplied by Intel cause the simulator to get a
segmentation violation, perhaps indicating that whomever wrote the
simulator did not understand the flush instruction, either :-)
I'd appreciate commentary from anyone in the know about what the
flush instruction really does, why we might be having problems, and
why the documentation claims that a cache flush area "not used to
store data" is needed.
Thanks,
--
Jon Leech (leech@cs.unc.edu) __@/
``Nuclear fusion, the promise of limitless energy from sea water
or something, has been just around the corner ever since World War
II and is still just around the corner.'' - David GoodsteinDon_A_Corbitt@cup.portal.com (07/17/90)
[question about using i860 FLUSH instruction] > Since we are running a single process in supervisor mode, the > caution about task switches should not apply. What we do is use the > address of the data buffer to be sent in the flush instruction, and > only flush a number of cache blocks corresponding to the message > length. > > I'd appreciate commentary from anyone in the know about what the > flush instruction really does, why we might be having problems, and > why the documentation claims that a cache flush area "not used to > store data" is needed. > Jon Leech (leech@cs.unc.edu) __@/ I don't _know_ the answer to this, but my theory is that the i860 flushes the cache by 'loading' data into the required cache block. I expect that FLUSH is really FLD that doesn't cause any memory reads. This is why they want the address of an unused block of data - it is 'loading' data from that address, forcing out any other address. I think you should reserve a 4KB block of address space that you don't use for anything else, and flush with that. Just for the record, I have written a small VM kernel for the i860. This isn't just PRM speculation :-) --- Don_A_Corbitt@cup.portal.com Not a spokesperson for CrystalGraphics, Inc. Mail flames, post apologies. Support short .signatures, three lines max.
rbn@umd5.umd.edu (Ron Natalie) (07/18/90)
You must flush the entire cache on the 860. I'm not sure what you are trying to acheive by only trying to flush part of the cache. It is not FIFO. Second, there are allsorts of chip bug voodoos with regard to cache flush. Make sure that you have the erratta sheet for your processor. Third, if the message buffer can be put in a page in memory that you wouldn't want cached anyway, why not just leave the cache disabled on that page? -Ron
Don_A_Corbitt@cup.portal.com (07/18/90)
> You must flush the entire cache on the 860. I'm not sure what you > are trying to acheive by only trying to flush part of the cache. > It is not FIFO. Second, there are allsorts of chip bug voodoos > with regard to cache flush. Make sure that you have the erratta > sheet for your processor. Third, if the message buffer can be > put in a page in memory that you wouldn't want cached anyway, why > not just leave the cache disabled on that page? > > -Ron Although the PRM appears to be silent on this issue, the i860 Microprocessor Architecture book (Neal Margulis, Osborne-McGraw-Hill, ISBN 0-07-881645-9) says you can flush pieces of the cache, such as for self-modifying code. --- Don_A_Corbitt@cup.portal.com Not a spokesperson for CrystalGraphics, Inc. Mail flames, post apologies. Support short .signatures, three lines max.