jac@paul.rutgers.edu (Jonathan A. Chandross) (01/10/89)
mslater@cup.portal.com (Michael Z Slater) writes: >One particularly interesting aspect of the three versions of the 960 is >that, at this point, they are all the same chip! Intel doesn't like to >admit that, but I have it on good authority that it is true. In the future, >of course, they may create subset designs that don't have all the features, >and even now, all features may not be tested in the simpler "versions." >It seems that Intel is not documenting the MMU functions for commercial >users because they don't want to support those functions, and they don't >want the chip to be used in computers anyway -- the 960 is supposed to >be for embedded control. Nevertheless, Intel has UNIX running on the 960 >internally. My source for the following information is the designer of what later became the Intel 80960. When the 80960 was announced I pointed it out to someone I used to work with, saying something like "well, Intel's finally gone into the RISC business." He replied that, no, Intel was not going into the RISC business. He said that he recognized the chip as one of his designs, and it was no RISC chip. He told me that he was at Intel about five years ago and was part of a team that designed a very powerful fault tolerant machine. The central processors were very very CISCy and had a very parallel internal architecture. The I/O processor chips were single chip microcoded channel controllers which were far more powerful that the IOPs that Intel was selling at the time. Anyway, it seems that Intel shelved the project but decided that the processors could be sold on the open market. However, the processors made the 80386 look like the dinosaur it really is. This meant that the sales of the 80386 might be "negatively impacted" (to use Pentagon speak), an obvious no-no. So Intel decided to cut out most of the hardware on the data path, remove any architectural parallelism, and in general to cripple the chip in such a way that the sales of the 80386 were safe. This is why those amazing features keep "cropping up". It's not that those wily engineers at Intel are staying up late to put those features in; it's that the marketing folk are finally allowing them back in. Jonathan A. Chandross ARPA: jac@paul.rutgers.edu UUCP: rutgers!jac@paul.rutgers.edu
mbutts@mntgfx.mentor.com (Mike Butts) (01/14/89)
From article <Jan.9.23.41.33.1989.22919@paul.rutgers.edu>, by jac@paul.rutgers.edu (Jonathan A. Chandross): > He told me that he was at Intel about five years ago and was part of a team > that designed a very powerful fault tolerant machine. The central processors > were very very CISCy and had a very parallel internal architecture. The I/O > processor chips were single chip microcoded channel controllers which were far > more powerful that the IOPs that Intel was selling at the time. > > Anyway, it seems that Intel shelved the project but decided that the processors > could be sold on the open market. However, the processors made the 80386 look > like the dinosaur it really is. This meant that the sales of the 80386 might > be "negatively impacted" (to use Pentagon speak), an obvious no-no. > > So Intel decided to cut out most of the hardware on the data path, remove any > architectural parallelism, and in general to cripple the chip in such a way > that the sales of the 80386 were safe. > Rumor around here has it that the difference between the 80960 CPU chip and the CPU chip used in the new Biin (Intel/Siemens joint venture) fault-tolerant machines is one or two bond wires on the same die. -- Mike Butts, Research Engineer KC7IT 503-626-1302 Mentor Graphics Corp., 8500 SW Creekside Place, Beaverton OR 97005 ...!{sequent,tessi,apollo}!mntgfx!mbutts OR mbutts@pdx.MENTOR.COM These are my opinions, & not necessarily those of Mentor Graphics.