amit@umn-cs.UUCP (Neta Amit) (10/07/87)
We're are looking into a co-processor that takes over certain OS tasks.
Specifically, we're thinking about scheduling, interrupts and swaps.
Possibly deadlock resolution.
Any thoughts? References to the literature?
Thanx in advance,
--Neta Amit (amit@umn-cs.arpa or amit@umn-cs.cs.umn.edu)
University of Minnesota CSci
--
--Neta Amit (amit@umn-cs.arpa)
University of Minnesota CScieeproks@pyr.gatech.EDU (Robert Viduya) (10/08/87)
In article <2272@umn-cs.UUCP> amit@umn-cs.UUCP (Neta Amit) writes: >We're are looking into a co-processor that takes over certain OS tasks. >Specifically, we're thinking about scheduling, interrupts and swaps. >Possibly deadlock resolution. > >Any thoughts? References to the literature? > >Thanx in advance, > --Neta Amit (amit@umn-cs.arpa or amit@umn-cs.cs.umn.edu) > University of Minnesota CSci > >-- >--Neta Amit (amit@umn-cs.arpa) > University of Minnesota CSci I seem to recall some Intel literature about a co-processor to the iAPX-86 series that supported iRMX. I think it was called the 80130 or something like that. Check with Intel. -------------------------------------------------------------------------- K. J. Seefried iii School of Information and Computer Science P.O. Box 30104, Georgia Insitute of Technology, Atlanta Georgia, 30332 uucp: ...!{decvax,hplabs,ihnp4,linus,rutgers,seismo}!gatech!ken internet: ken@gatech.edu
jdu@ihopa.ATT.COM (John Unruh) (10/08/87)
In article <2272@umn-cs.UUCP>, amit@umn-cs.UUCP (Neta Amit) writes: > We're are looking into a co-processor that takes over certain OS tasks. > Specifically, we're thinking about scheduling, interrupts and swaps. > Possibly deadlock resolution. > > Any thoughts? References to the literature? If I remember correctly, many (if not all) of the CDC 6000 series computers used operating systems that ran mostly in the peripheral processors. This freed the CPU to crunch numbers. Some of these operating systems were fairly efficeint, but I never used one that was "nice" for an interactive user. They seemed to be very good at batch throughput. John Unruh ihnp4!ihlpk!jdu
grunwald@uiucdcsm.cs.uiuc.edu (10/09/87)
If I'm not mistaken, the Convex C-1 architecture has a PPU-like setup with 68000 based systems managing I/O & interrupt handling. Also, doesn't the Alliant FX have IOPs? Cybers have had PPUs built from barallel-processors for eons -- all I/O and context switching requests for Cybers was done by these. A local group (Computer Based Education research Lab -- a.k.a. PLATO) is building cyber-CPUs which use 68000s as PPUs. Even the lowly Intel 310 has a quasi-OS processor -- the ethernet board in our system manages the rlogin & telnet sessions, freeing the main CPU of interrupts.
ron@topaz.rutgers.edu (Ron Natalie) (10/11/87)
> Also, doesn't the Alliant FX have IOPs?
Actually, the same code (more or less) can run on the IOPs in
the Alliant as in the CE's. This is because they used the same
baseline 68000 instruction set in the CE's and real 68000 series
processors in the IOP's.dennisg@felix.UUCP (Dennis Griesser) (10/14/87)
In article <2272@umn-cs.UUCP> amit@umn-cs.UUCP (Neta Amit) writes: >We're are looking into a co-processor that takes over certain OS tasks. >Specifically, we're thinking about scheduling, interrupts and swaps. >Possibly deadlock resolution. In article <4171@pyr.gatech.EDU> eeproks@pyr.UUCP (Ken Seefried iii) writes: >I seem to recall some Intel literature about a co-processor to the iAPX-86 >series that supported iRMX. I think it was called the 80130 or something >like that. Check with Intel. But you won't like it. If I remember correctly, this part is NOT a co-processor, but a bundle of peripheral hardware, like a Priority Interrupt Controller and some timers, and some firmware all in one chip. Intel seems to have quietly dropped the thing. I couldn't find more than a passing reference to it in a quick pass over the Intel catalogs. But hey, there are a lot of Intel folks on the net. Perhaps one of them could provide us with more info...
adam@its63b.ed.ac.uk (ERCF02 Adam Hamilton) (10/14/87)
ICL, the British manufacturer, sells a highly specialised co-processor with most of its database machine sales. The device is called CAFS (Content Addressable File Store). It is a special disc controller containing purpose built micro- processor devices, which can scan data AS IT COMES OFF THE DISC for particular values. Only those records which meet the current criteria are passed on to the main processor. The idea is that a program requests all records from a database which match certain values (fuzzy matching is also supported). The CAFS controller scans the whole database/disc and passes on appropriate records. The CAFS device is fully compatible with normal format discs and database records. The device was first invented in the early 70s and hung around waiting to be used. It is now very successful to the point that it is standard for most ICL database installations to have one or more as part of the configuration. Sorry I can't give references. It also doesn't do sorting, which was the original query.
aglew@ccvaxa.UUCP (10/28/87)
..> adam@its63b.ed.ac.uk writes about ICL's CAFS, a disk controller
..> which filters data as it comes off the disk, before passing it
..> to the main processor.
Pardon me for a bit of advertisement, but Gould also sells such a device,
called a HYPERSEARCH board, which filters data as the disk revolves.
It can be used under UNIX, and has great potential for grepping on
documentation :-).
As a matter of fact, it may have been done by the same Scottish
company that did ICL's board.
These are not, however, content addressible memories in the sense of
cache controllers and the AMD file store. They are, rather, filters on
the rapid flow of data off the disk, that reduce CPU involvement in
processing. Although they probably contain some associative component,
similar devices (for PCs, for example), do not, and still have advantages.
There seems to be a transatlantic difference in the meaning ascribed to
"associative memory" or "content addressible memory" - or maybe the
difference is between subfields of computer engineering. I usually think
of an associative memory as one that you present part of a data item to,
and it returns the rest of the data item - with parallel match circuitry,
not with a microsequencer going and doing a sequential or hashed search
on the internal representation. Papers from Europe or in databases tend
to talk about associative memories as being the black box - without
caring about how the internal search is done.
Neither definition is right or wrong. It's just useful to know
what somebody is thinking of when he says "content addressible memory".
I know that I nearly flipped when I read a Japanese article talking about
a 64M-element associative memory...
Andy "Krazy" Glew. Gould CSD-Urbana. USEnet: ihnp4!uiucdcs!ccvaxa!aglew
1101 E. University, Urbana, IL 61801 ARPAnet: aglew@gswd-vms.arpa
I always felt that disclaimers were silly and affected, but there are people
who let themselves be affected by silly things, so: my opinions are my own,
and not the opinions of my employer, or any other organisation with which I am
affiliated. I indicate my employer only so that other people may account for
any possible bias I may have towards my employer's products or systems.