reiter@endor.harvard.edu (Ehud Reiter) (08/27/87)
In article <630@winchester.UUCP> mash@winchester.UUCP (John Mashey) writes: >mips MHz MHz/mips CPU / System >6 22.2 3.7 VAX 8700 > >This is a good illustration of the well-understood fact that >you can keep the cycles/mips ratio pretty low, even for a clearly >non-RISC architecture. The above figure is a bit misleading, as "mips" on a VAX bear little relationship to instruction throughput. About a year ago, I heard a talk by a DEC engineer who said the instruction throughput on a pipelined VAX 8700 is about one instruction per 8 cycles. This doesn't seem too impressive, since the throughput on a non-pipelined VAX-11/780 is one instruction per 10 cycles. I asked the engineer why they even bothered pipelining if they only increased the instruction/cycle throughput by 20%, and his response was that pipelining let them shorten the cycle time (i.e. a pipelined 8700 cycle does less work than a non-pipelined 780 cycle??). The above numbers may be a bit off (the talk was a while ago), but it definitely was the case that the instruction/cycle numbers for the 8700 were only a bit better than the numbers for the 780. Ehud Reiter reiter@harvard (ARPA,BITNET,UUCP) reiter@harvard.harvard.EDU (new ARPA)
mash@mips.UUCP (08/28/87)
In article <2765@husc6.UUCP> reiter@harvard.UUCP (Ehud Reiter) writes: >In article <630@winchester.UUCP> mash@winchester.UUCP (John Mashey) writes: >>mips MHz MHz/mips CPU / System >>6 22.2 3.7 VAX 8700 >The above figure is a bit misleading, as "mips" on a VAX bear little >relationship to instruction throughput. About a year ago, I heard a -------absolutely right! see below. >talk by a DEC engineer who said the instruction throughput on a pipelined VAX >8700 is about one instruction per 8 cycles. This doesn't seem too impressive, >since the throughput on a non-pipelined VAX-11/780 is one instruction per >10 cycles. I asked the engineer why they even bothered pipelining if they >only increased the instruction/cycle throughput by 20%, and his response was >that pipelining let them shorten the cycle time (i.e. a pipelined 8700 cycle >does less work than a non-pipelined 780 cycle??). (This is perfectly reasonable). This all makes perfect sense, and is one of the reasons we try to normalize to externally visible & measureable things, like actual performance, not trying to count instructions. The trouble with the latter is that the only people who really know are the people who build their own computers. Cycles/instruction is of extreme interest to such folks, but its very hard to get to from outside. Quick, what's the cycles/instruction of your favorite machine? How do you know? On the other hand, what's the mips (relative to 11/780 == 1) rating, and the cycles/mips, at least on any chosen benchmark? (a bit easier) In particular, let us recall that the table for an 11/780 is: >>mips MHz MHz/mips CPU / System >>1 5 5 VAX 11/780 And yet, it is well known as Ehud says, that the 11/780 takes 10 (or maybe 11) cycles / VAX instruction [a good analysis can be found in one of Doug Clark's papers, I think the one in April 1982 SIGARCH]). What's going on is that an 11/780 is actually a .5(some kind of mips) machine, i.e., it does 500,000 actual vax instructions/second, not 1 million. However, since many people call the 780 "1-mips" or "1-vmips" or "1-vax-mips", it's hard to know what (some kind of mips) is! What this means is that a vax 11/780 instruction is worth 2 "mythical mips" instructions, weirdly enough, each of which happens to be pretty equivalent to the sort of instructions found in RISC machines of the Precision/MIPS/SPARC ilk. Thus, in reality: vax-mips aren't, they're really million (RISC-like) ips -- -john mashey DISCLAIMER: <generic disclaimer, I speak for me only, etc> UUCP: {decvax,ucbvax,ihnp4}!decwrl!mips!mash OR mash@mips.com DDD: 408-991-0253 or 408-720-1700, x253 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086