schow@bnr-public.uucp (Stanley Chow) (05/08/89)
In article <1989May4.161046.21510@utzoo.uucp> henry@utzoo.uucp (Henry Spencer) writes: > >Consider a well-built RISC, with an instruction cache, executing an >interpreter that fetches bytes from memory and interprets them as if >they were, say, 8086 instructions. Assuming that the interpreter fits >in the I-cache, in what way does this differ from the WISC idea? > There can be major differences. First, we need to define what you mean by "well-built RISC'. I assume you mean something that is optimized for cycle time with simple instructions - along the lines of currently RISC chips. In my mind, a WISC micro-engine would have many parallel execution units explicitly under micro-code control. The macro-instructions would be substantially "bigger" than RISC instructions, perhaps bigger even than the dreaded VAX instructions. It seems clear to me that the optimal WISC micro-engine will have a very different instruction set from the RISC engine. A WISC machine can also have a bigger/faster micro-code space. Tag RAM is not needed and the micro-sequence usually have a much better idea of what is happening in the code, so pipelining is improved. (Probably for both the micro- and macro- pipes). Stanley Chow BitNet: schow@BNR.CA BNR UUCP: ..!psuvax1!BNR.CA.bitnet!schow (613) 763-2831 ..!utgpu!bnr-vpa!bnr-fos!schow%bnr-public I am just a small cog in a big machine. I don't represent nobody.