ram@alpha.UUCP (04/01/87)
Nice to be back and read a few weeks backlog of news. Wow, 20+ responses
within a week. I did not have the patience to read all
of these. Not only that, the subject strayed into HP and 386 architectures
and all previous notes had been efficiently put away by our archiver.
So I really don't know what happened except for some sketchy
recollections. Anyway some of the topics:
1. Confusion and correction on some issues
a. what does 64 bit represent - data path
.. I was not brought up in 808X generation
b. mP? yes
2. Packaging is going to be a great problem. Am29000 has 169
pins. My rule of thumb (before I read the no. of pins for
Am29000) was 3*data-path size (upper bound). Obviously
that does not hold. Looks like something of
the order of 5. In which case 325+ pins in a single package
is going to end up as a topsturvy porcupine .
Hence a single chip 64 bit general purpose processor may not be
advisable.
3. Even if there is an 64bit data path, there are other trade-offs
Whether a FPU should be on-chip or off-ship? (assuming your
device technology goes down to tenths of a micron) Hence
more si real estate requirements arise as the internal
BW is jumped by an order of 2. If you go off-chip (For FPU
and other functional blocks), then the speed and excessive
on-chip BW will have to be utilized.
4. Instead of 64-bit processors we may see a dedicated set of
processors for various applications. Something like
a general CPU alongwith say a FPU, graphics chip and other
paraphrenelia like Lisp, Smalltalk if needed.
How about this? An external data bus of 64 bits and
internal datapath (for the CPU) of 32. The FPU could
be 64 bits so would fay's and landman's CORDIC chip.
Maybe the graphics chip too. A heterogenous set of processors
(not really parallel processing. Dedicated hardware for
special functions). I have always wondered why the 808? had an
internal datapath size twice that of external data bus.
My understanding is memory access will always be the pain...
why not reverse that comfiguration. (assume the external
line width is reasonable).
5. Given the above configuration, (oh my god there are so many tricks
that comes to mind) we could also have a 32 bit processor-processor
path (a ring maybe) to share data amongst processors and leave
the central bus for memory fetches alone. Well all these are
nice (or wrong) fancy thoughts. Comments on these impromptu
thoughts?
Renu Raman
...ihnp4!nucsrl!ram