mark@mips.COM (Mark G. Johnson) (01/08/89)
In article <296@quick.COM> srg@quick.COM (Spencer Garrett) writes: >Anybody got a reference for the DARPA Microprocessor without >Interlocked Pipe Stages (or MIPS) Core Instruction Set >Architecture specification? About a year ago, two papers were published revealing Gallium Arsenide microprocessors. Both were sponsored by DARPA and both used the "core-MIPS" instruction set architecture. One was from Rockwell and used junction field-effect transistors (MESFETs), and the other, from Texas Instruments, used heterojunction bipolar transistors: Gauthier, R. V., et al, "A 150MOPS GaAs 8b Slice Processor", Digest of Technical Papers, 1988 International Solid State Circuts Conference (ISSCC), February 17, 1988, pp. 32-33. Whitmire, D. A., et al, "A 32b GaAs RISC Microprocessor", Digest of Technical Papers, 1988 International Solid State Circuts Conference (ISSCC), February 17, 1988, pp. 34-35. Incidentally, don't be fooled by the trade press claims that the T.I. device uses "I2L" logic; it doesn't. There aren't any injectors, hence "Integrated Injection Logic (I2L)" is a misnomer. Instead of bipolar PNP injectors, the T.I. device employs passive resistor pullups. Multi-collector drivers (pulldowns) are used. -- -- Mark Johnson MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086 ...!decwrl!mips!mark (408) 991-0208