lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay) (02/11/90)
In article <1518@motmpl.UUCP> ron@motmpl.UUCP (Ron Widell) writes: >The MC88200 has been clean since Jan, '89. It is also currently being >processed in a 1.2 micron DLM technology. > >Both devices are scheduled for imminent release in 1.0 micron geometries, >so we may soon see 40MHz (Maybe even 50?) devices. "Electronics" Jan 1990, P.82: "With its Mosaic IV process, Motorola expects to push performance on a BiCMOS version of its 88000 chip to as high as 100 MHz." Neat, if it's true. One advantage of the 88100 is that you certainly expect product announcements to also announce a fast enough cache (the 88200). The "scalable" SPARC hasn't advanced much in the last year - there's an 80 MHz ECL chip, and 40 MHz CMOS, but no boxes faster than 33 MHz (and from Solbourne at that!) Presumably it's just really challenging to build fast caches, and the Ross/Cypress cache chip isn't here yet. Is it overdue? It would be nice to see working R6000 boxes, just to prove that high clock rates aren't hype. -- Don D.C.Lindsay Carnegie Mellon Computer Science