mark@mips.COM (Mark G. Johnson) (10/11/89)
The SPEC benchmarks (sources) have been officially released, and about
a dozen machines' results (their "SPECmark" ratings) have been published;
see, for example, EETimes Oct 9, page 1.
One of the machines that did quite well* was the Apollo DN10000, which has,
among other things, multiple instruction issue (superscalar) and a
"FP multiply and add" instruction. {was this the inspiration for the
i860 which appeared 2 years later? :-)}
So this makes me wonder, how will a Serious multiple-instruction-issue
machine like a VLIW perform on SPECmarks? Does anybody out there have
SPEC measurements on a Multiflow computer, preferably one of the big
bohunker maxi-config models with lots of parallel execution units?
Measured *data* preferred (vs. conjecture/opinion).
Thanks in advance.
* one or two plain-vanilla scalar
machines SPECmarked about as fast
or slightly faster than the DN10000
--
-- Mark Johnson
MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086
(408) 991-0208 mark@mips.com {or ...!decwrl!mips!mark}aglew@urbana.mcd.mot.com (Andy-Krazy-Glew) (10/17/89)
>One of the machines that did quite well* was the Apollo DN10000, which has, >among other things, multiple instruction issue (superscalar) and a >"FP multiply and add" instruction. {was this the inspiration for the >i860 which appeared 2 years later? :-)} Urghh.... What do you mean by "superscalar"? I understood it, at first, to mean "parallel dispatch of instructions from an instruction set with sequential semantics, after first having checked dependencies". I think it was in N. Jouppi's paper --- but come to think of it, that paper contrasted superscalar vs. superpipelined, and did seem to imply things about VLIW style parallel instruction dispatch. May I suggest terminology: *Parallel instruction dispatch* dispatching more than one instruction per cycle. May be done: *With Interlocks* assuming an underlying serial model *Without Interlocks* *Parallel Instruction Execution* Executing more than one instruction per cycle. These instructions may be parallel dispatched, or serially dispatched. Pipelining is a simple example of parallel instruction execution, although it is more interesting to consider non-pipelined versions, where instructions may cross, etc. Again, may be w/wo interlocks *Parallel Instruction Semantics* Imply that several different operations may be specified in the same instruction. Implies no interlocks. Most of the recent VLIW-style announcements are in this category. There are serial versions of each of the above. Obviously, they may be combined. Eg. conceivably a TRACE-28 could do parallel dispatch and execution of a TRACE-7 program, given suitable dependency checks. Serial instruction dispatch may be combined with parallel instruction execution. This was, eg., Tomasulo's original algorithm. It is not unimaginable that the dispatch unit might be clocked faster than the execution unit, so that a several instruction parcel that can be executed in parallel, in a single execution unit cycle, might be built up from a serial instruction set by a serial dispatch unit in overdrive. There are some interesting tradeoffs here. Andy "Krazy" Glew, Motorola MCD, aglew@urbana.mcd.mot.com 1101 E. University, Urbana, IL 61801, USA. {uunet!,}uiucuxc!udc!aglew My opinions are my own; I indicate my company only so that the reader may account for any possible bias I may have towards our products. -- Andy "Krazy" Glew, Motorola MCD, aglew@urbana.mcd.mot.com 1101 E. University, Urbana, IL 61801, USA. {uunet!,}uiucuxc!udc!aglew My opinions are my own; I indicate my company only so that the reader may account for any possible bias I may have towards our products.