csc@orchid.UUCP (09/15/87)
I've been reading a book (Systems Design with Advanced Microprocessors, John Freer, 1987) which mentioned the following in its rundown of 68020 relatives: ... > d) MC68030 which integrates an MC68020, a subset of the MC68851 > programmable memory management unit (using a 22-entry translation > lookahead [sic] buffer) and separate 256-byte instruction and data caches. > Performance is thus increased by 1.5 to 2.5 times when these new facilities > are used but the improvement in performance is approximately 50 per > cent for MC68020 compiled code run on a 20 MHz MC68030. The cache > is reorganized as 16 entries of four 32-bit words, the same as the Z80000, > and the internal bandwidth is increased to 80 Mbyte/s. Other improve- > ments include 1.2 um CHMOS (300 000 transistors) and a burst mode > for filling the caches from memory. > > e) A RISC version of the MC68020 is also planned and the future > MC68040 is expected to have a larger data bus and internal 128-bit regis- > ters. I thought I'd throw this out for criticism and comment. -Colin Plumb (ccplumb@watmath) Note: My account doesn't exist yet, so I'm posting from another.
roy@forbrk.UUCP (Roy Gordon) (09/17/87)
In article <10652@orchid.waterloo.edu> Please don't. writes: >I've been reading a book (Systems Design with Advanced Microprocessors, >John Freer, 1987) which mentioned the following in its rundown of 68020 >relatives: > >... > > d) MC68030 which integrates an MC68020, a subset of the MC68851 > > programmable memory management unit (using a 22-entry translation > > lookahead [sic] buffer) and separate 256-byte instruction and data caches. The 68030's PMMU is not a subset of the MC68851. The 68030's PMMU has two Transparent Translation Registers (TTR) not found on the 68851. The registers allow cache hits for an entire range of addresses for which the logical and physical addresses are the same. In particular, these registers may be adequate for mapping the Unix kernel and the i/o space of a system, except for the u-block. Address hits via the TTR's are cache hits but do not result in entries in the 68030's 22-entry cache. In effect, the kernel and i/o space can now have perfect locality, except for the u-block. On the 68851 although contiguous addresses can be specified at high levels of the translation tree, so that lower level page tables are not needed. However, each time a page is accessed within such a space,an entry for that page is placed in the translation cache. The lack of kernel locality will thus result in many entries in the address translation cache, causing more misses, more flushes of the cache, etc., etc. However, limiting the 68030's PMMU address translation cache to 22 entries and no process tag i.d.'s has to be a giant step backward.