tmandadi@uoregon.uoregon.edu (tilak mandadi) (12/22/88)
Can somebody explain me why we can't have on chip cache in RISCs using GaA technology ? thanks.
lindsay@k.gp.cs.cmu.edu (Donald Lindsay) (12/22/88)
In article <3417@uoregon.uoregon.edu> tmandadi@uoregon.uoregon.edu (tilak mandadi) writes: > Can somebody explain me why we can't have on chip cache in RISCs using > GaA technology ? thanks. If you mean gallium arsenide (GaAs), then the answer is that it isn't available yet. This is a very exciting year for GaAs fans. Several players have just announced gate arrays at the 10,000 gate level. That's enormous by the standards of a year or two ago. Getting the technology into production just took a lot more struggle than some of us predicted. In time, someone (or lots of people) will build the chip you asked for. There's no reason why 500 MHz isn't achievable. But you'll have to wait. -- Don lindsay@k.gp.cs.cmu.edu CMU Computer Science --
landman%hanami@Sun.COM (Howard A. Landman) (12/28/88)
In article <3417@uoregon.uoregon.edu> tmandadi@uoregon.uoregon.edu (tilak mandadi) writes: > Can somebody explain me why we can't have on chip cache in RISCs using > GaA technology ? thanks. Yield decays exponentially with chip area (at the upper limit). Current GaAs fabrication doesn't allow economical production of chips that complex. Give it a few more years. Howard A. Landman landman@hanami.sun.com