mark@mips.COM (Mark G. Johnson) (10/19/89)
In article <1T9NpG#464lr4=eric@snark.uu.net> eric@snark.uu.net (Eric S. Raymond) writes: >In <1989Oct17.154651.16073@utzoo.uucp> Henry Spencer wrote: >> (One of the gems of my collection is an unintentionally-hilarious paper >> from an IEEE conference proceedings that proves, in some detail, that it >> is impossible to build 64Kb DRAMs with optical lithography.) > >O.K., now please tell us which limiting assumption went wrong and why. I don't have that one, but I do have one that sez you can't build a 1Mbit DRAM the same way you built a 64K. (Tell that to Toshiba and NEC who did exactly that!) In particular they predict the death of the planar-capacitor memcell: 1984 Digest of Technical Papers, International Solid-State Circuits Conference (ISSCC), pp. 160-161, "Physical Limits of VLSI DRAMs" Assumptions in the paper that didn't prove out in commercial devices 1. For a memory with 2^n bits, there will be no more than 2^(n/2) sense amplifiers, i.e. no memory block sub-partitioning. 2. Sense amplifier offset voltage is 20mV. 3. Cell layout will be 6*f*f units of area, where f== minimum featuresize 4. There will be no improvement in processing and/or packaging technology which lowers the flux rate of alpha particles (causing soft errors). Thus polyimide die coatings and low-alpha plastic mold compounds were not predicted (but did, in real life, happen). (of course these assumptions weren't explicitly called out in the paper in a paragraph labelled "Assumptions"; you have to extract them by reading the "what's possible" material and deducing why they said what they said.) -- -- Mark Johnson MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086 (408) 991-0208 mark@mips.com {or ...!decwrl!mips!mark}