ram@nucsrl.UUCP (03/06/87)
Now that we have huge register files (In RISCs, Vector CPUs) how is
the organization of these register files different say from a generic RISC
to a generic VECTOR cpu?.
Most microprocessors regs have single port write and dual ported read(as
an ALU can take 2 args and outputs one). Given a large register
bank, a multiple functional unit CPU, we need more (probably not!)
than dual porting read ports. That would not be the case when concurrent
read is not permissible. But if there is a smart compiler/hardware
that figures out when a sequence such as this goes
I1: R1=R2*R3
I2: R80=R1*R2
I3: R2=R3*R5
I4: R125=R124*R3
I4 can be pushed ahead if any of the previous instructions are
waiting for some resource to be freed. In which case we don't lock
a register if it has been annotated "read" only.
Now, the size of the word and performance dictate on the register cell
requirements. What is the complexity of building such register files.
(I am purposely vague about complexity as I don't know how to quantify this
in terms of cost, % of CPU VLSI area etc....)
In most of these cases additional tag bits are needed for certain specific
purposes. From purely practical design viewpoints, what are the constraints
imposed on the size of a register (word-size + tag bits) and also on the
number of registers.
The size of the internal data path and regsiter-register-ALU
intrachip communication could also give rise to bottlenecks. if
we have a multiple functional unit CPU, the bus contention within the chip is
a problem. Having just a pair of buses to interconnect the register bank
with a multiple functional unit CPU is problematic. Do we have to
stick with a pair of buses (due to area restrictions) or are there any
tricks to go around this.
I wonder how this was done with the CRAYs, CYBERs, ETAs .......
renu raman
...ihnp4!nucsrl!ram
Northwestern University Comp. Sci.
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