niehaus@tempo.cs.umass.EDU (Douglas Niehaus) (04/02/91)
Ok, so I am reading the RS2000 book by Kane, and I have felt like I understood what was going on, but I have a nagging question left. Branch delay iand load delay slots are one instruction in length, which I can deal with as long as what is being fetched from memory is in the cache, but what happens for a cache miss? I can deduce, I think, that on a miss the who processor must get frozen until the fetch from main memory is finished, or else the single delay slot would not be enough. Is this correct? If not, what DOES happen? If so, just how is it done? Douglas Niehaus niehaus@tempo.cs.umass.edu
randy@imagen.com (randy scofield) (04/04/91)
In article <28677@dime.cs.umass.edu> niehaus@tempo.cs.umass.EDU (Douglas Niehaus) writes: >Ok, so I am reading the RS2000 book by Kane, and I have felt like I understood >what was going on, but I have a nagging question left. > >Branch delay iand load delay slots are one instruction in length, which I can deal with as long >as what is being fetched from memory is in the cache, but what happens for a cache miss? > >I can deduce, I think, that on a miss the who processor must get frozen until the >fetch from main memory is finished, or else the single delay slot would not be enough. >Is this correct? If not, what DOES happen? If so, just how is it done? > >Douglas Niehaus >niehaus@tempo.cs.umass.edu The processor is stalled on all cache misses. The R2000 will get the data from memory, stick it in the cache and then proceed. All pipe stages are frozen during the stall. The R3000 will do a block refill of 4/8/16/32 words as oppossed to the single read of the R2000. The block refill will hopefully fetch the data that will stop the next few stalls from occurring. Hope this answers your question. Randy