kuszewsk@euler.biology.yale.edu (John Kuszewski) (05/14/91)
Hi! Can anyone send me some good references on VLIW? On a related note, Teraplex, Inc. (Champaign, IL) was working on a VLIW-based processor called the "MISC" (minimal inst. set computing) chip. They seem to have given up. Does anyone have any more details? --- John Kuszewski kuszewsk@euler.biology.yale.edu
hrubin@pop.stat.purdue.edu (Herman Rubin) (05/14/91)
In article <1991May13.192955.15766@cs.yale.edu>, kuszewsk@euler.biology.yale.edu (John Kuszewski) writes: > Hi! > > Can anyone send me some good references on VLIW? On a related note, Teraplex, > Inc. (Champaign, IL) was working on a VLIW-based processor called the "MISC" > (minimal inst. set computing) chip. They seem to have given up. Does anyone > have any more details? I echo this point. I would like to see just what these architectures were, not merely *STONES or other similar stuff. This is comp.arch, and the complete instruction set is the architecture. -- Herman Rubin, Dept. of Statistics, Purdue Univ., West Lafayette IN47907-1399 Phone: (317)494-6054 hrubin@l.cc.purdue.edu (Internet, bitnet) {purdue,pur-ee}!l.cc!hrubin(UUCP)
bengtl@maths.lth.se (Bengt Larsson) (05/15/91)
In article <12293@mentor.cc.purdue.edu> hrubin@pop.stat.purdue.edu (Herman Rubin) writes: >I echo this point. I would like to see just what these architectures were, >not merely *STONES or other similar stuff. This is comp.arch, and the >complete instruction set is the architecture. Then you should propose actual instruction sets in your examples, instead of pointing to similarities with auto gear transmissions. Bengt Larsson. -- Bengt Larsson - Dep. of Math. Statistics, Lund University, Sweden Internet: bengtl@maths.lth.se SUNET: TYCHE::BENGT_L
astevens@acorn.co.uk (Ashley Stevens) (05/16/91)
In article <1991May13.192955.15766@cs.yale.edu> kuszewsk@euler.biology.yale.edu (John Kuszewski) writes: >Hi! > >Can anyone send me some good references on VLIW? On a related note, Teraplex, >Inc. (Champaign, IL) was working on a VLIW-based processor called the "MISC" >(minimal inst. set computing) chip. They seem to have given up. Does anyone >have any more details? >From 'Electronics Times' May 16th :- 'Teraplex, the US processor architect, has closed its doors. It shut just four weeks before delivering the design of its minimum instruction set computing (MISC) chip to its foundry Atmel. Jeff Glickman, Teraplex' chief scientist, said it was unable to get the $2M it needed to complete the project "largely due to the vacuum caused the Desert Storm". The MISC chip promised high speed instruction level emulation of microprocessors like the Sparc, Mips, and Intel i86 series. It did this by using nine 'atomic' instructions to build up more complex instructions.' ___________________________________________________________________ Ashley Stevens astevens@acorn.co.uk Acorn Computers, 645 Newmarket Rd, Cambridge, UK. Tel.(0223) 214411
rmbult01@ulkyvx.bitnet (Robert M. Bultman) (05/25/91)
From: kuszewsk@euler.biology.yale.edu (John Kuszewski) Date: 13 May 91 19:29:55 GMT > >Hi! > >Can anyone send me some good references on VLIW? On a related note, >Teraplex, >Inc. (Champaign, IL) was working on a VLIW-based processor called the "MISC" >(minimal inst. set computing) chip. They seem to have given up. Does anyone >have any more details? > >--- >John Kuszewski >kuszewsk@euler.biology.yale.edu VLIW refs: ========== Any early work by Josh Fisher circa 1977-1985 from Yale. Several papers. A compiler for the Yale ELI VLIW: John R. Ellis, 1986, _Bulldog: A Compiler for VLIW Architectures_, Cambridge, Mass., The MIT Press Excellent in-depth article describing Multiflow Trace: Robert Colwell, et al., "A VLIW Architecture for a Trace Scheduling Compiler", IEEE Transactions on Computers, Vol 37, No. 8, p967-969 Patterson and Hennessy discuss a VLIW extension to their DLX machine. However, they do not look at it favorably (if I read between the lines correctly (oh, this is in Computer Architecture, A Quantitative Approach, of course)). FPS machines: Alan Charlesworth, "An Approach to Scientific Array Processing: The Architectural Design of the AP-120B/FPS-164 Family", IEEE Computer, 1981, vol 14, no 8 (sept), 18-27 Woodrow Wittmayer, "Array Processor Provides High Throughput Rates", IEEE Computer, 1978, march, 93-100 Good coverage of AP-120B: Kai Hwang and Faye Briggs, _Computer Architecture and parallel Processing_, 1984 (Note on the AP-120B and FPS-164: I am not sure if these qualify as VLIWs, although I am pretty sure they are. They are back-end processors attached to a host computer. I believe that box (if that is correct) itself is a full-fledged VLIW, and that the host uses the processor by giving high-level commands, if you will, and the processor executes them by executing a hand-coded, highly optimized sort of subroutine in its native language. The AP-120B has(had) only a Multiplier and a Divider (floating point that is), so transcendentals and such would have to be handled be a subroutine of some sort. I can post a more detailed description at a later date, but I suggest reading the Hwang and Briggs ref first, then one or both of the other articles.) Ellis mentions a system called the MARS-432, although I have not found any published literature on this system. There is a description of an ECL version of the Multiflow Trace that was given at Supercomputing '90. I have not seen this reference. Trace scheduling is important for VLIWs (exploitation of fine-grained parallelism). See Ellis and Fisher papers for this. I believe that several other compilation/scheduling methods arose from trace: percolation scheduling is one. (I realize that some of this is a bit sketchy, but I am in the process of moving, and my notes are packed away.) Robert M. Bultman Speed Scientific School University of Louisville
wolfe@vw.ece.cmu.edu (Andrew Wolfe) (06/05/91)
Also see: Labrousse & Slavenberg: CREATE-LIFE: A Modular Design Approach for High Performance ASIC's COMPCON '90 and Rau: The Cydra 5 Departmental Supercomputer COMPUTER - January, 1989 Also... If you want a glimpse of the future... :) see Wolfe: A Variable Instruction Stream Extension to the VLIW Architecture ASPLOS IV