lpress@venera.isi.edu (Laurence I. Press) (07/25/88)
The Precursors of Personal Computing
I am compiling an anthology of historical papers which laid the
groundwork for today's workstations and personal computers. The
following list is preliminary, based mostly on personal
recollection and a little library research and suggestions from
others.
About half of the items in the list are papers I have copies of,
and about half are entries like "a paper by x" or "something on
topic x," so I would like your feedback. Are there topic areas
which have been overlooked; are there systems, programs or people
which have been overlooked; do you recall (even vaguely)
particular papers, reports or articles which should be included?
If you are interested in the good old days, let me know and I
will keep you updated on the list as it grows. Here is the list
as it stands today:
Personal Computers, The Beginning
A Preliminary List of Topics and Papers
1. The Concept of Personal Computing
Vannevar Bush, As We May Think, Atlantic Monthly, July, 1945
JCR Licklider, Man-Computer Symbiosis, IRE Transactions on Human
Factors in Electronics, March 1960
Douglas Englebart, A Research Center for Augmenting Human
Intellect, 1968 FJCC
Tom Steel, After Timesharing, What? SDC internal working paper,
8/21/67
Fred Gruenberger, "Are Small, Free-Standing Computers Here To
Stay?" Datamation, April, 1966, pp 67-8
2. Computers for the Masses -- The Vision of Computers as Tools
for non-technical People
Alan Kay, A Personal Computer for Children of All Ages, 1972 ACM
National Conference
Robert L. Albrecht, A Modern Day Medicine Show, Datamation,
July, 1963
something by Kemeny and Kurtz discussing the value of
including programming and computer literacy as part of a
liberal education
Roberts and Yates, ALTAIR 8800, Popular Electronics, January,
1975
Jim Warren -- either his IEEE or NCC personal computing survey
of 1976
something from Albrecht's PCC Newspaper or perhaps an early
Dr. Dobbs
something by Ted Nelson, David Ahl or Steve Jobs
3. Early Interactive Applications
A. Graphics
Ivan Sutherland, Sketchpad, a Man-Machine Graphical
Communication System, SJCC, 1963
Steven Anson Coons, An Outline of the Requirements for a
Computer-Aided Design System, 1963 SJCC
something from GE?
B. Text Processing
something on the "Expensive Typewriter" mentioned in Levy's
Hackers or other screen oriented text processing system
perhaps another paper from Englebart's lab
something on IBM's Administrative Terminal System for the
1440 (1965?) or their announcement of the Magnetic Tape
Selectric Typewriter (1964?)
an early paper from the Writer's Workbench at AT&T
C. Spreadsheet
A paper on one of the early time-shared financial planning
languages -- was there one called FPL at MIT?
D. DB and File Management
paper on RPG, FARGO or other early packages for conversion
of punched card applications
papers on early systems at GE, Informatics and SDC
papers on early codasyl work
(papers and also old ads and press release photos)
E. Engineering and Miscellaneous
Everett, et al, SAGE - A Data-Processing System for Air
Defense, 1957 EJCC
A Culler and Fried paper or Culler and Huff, Solution for
Non-Linear Integral Equations Using On-Line Control, 1962
SJCC
4. Early Stand-Alone Machines
Mitchel and Olsen, TX-0: A Transistor Computer (1956 EJCC)
Frankovich and Peterson, A Functional Description of the Lincoln
TX-2 Computer, 1957 WJCC (several other papers on the TX-2 in the
same proceedings)
RR Everett, The Whirlwind I Computer, AIEE-IRE Conference, 1951
Clark and Molnar, A Description of the LINC. In Computers in
Biomedical Research, I. R. W. Stacy and B. D. Waxman (eds),
Academic Press, New York, 1965
Xerox ALTO paper -- internal or published
perhaps something on early commercial products which were used
in single-user mode, for example, the Royal McBee LGP-30, IBM
1620, Bendix G-15, DEC PDP-8, Wang and HP programmable
calculators, IBM 5100 or Three Rivers PERQ
5. Timesharing -- Interactive Computing for the Masses, and the
Idea of a Community of Users sharing Data, Programs and
Resources
Christopher Strachey, Timesharing in Large Fast Computers,
UNESCO, 1960
McCarthy, J., et al, A Timesharing Debugging System for Small
Computers, 1963 SJCC
Jack Dennis, A Multi-user Computation Facility for Education and
Research, CACM, 9/64
Corbato, et al, An Experimental Timesharing System, 1962 SJCC
Schwartz, et al, A General-Purpose Time-Sharing System, 1964 SJCC
Edward Fredkin, The Time Sharing of Computers, Computers and
Automation, November, 1963
6. Communication -- Extending the User Community Beyond the
Timesharing System
Early technology, e.g. Fry, Stibitz, and Williams, Complex
Computer paper, 1940, Baran paper from RAND, Paper on SDC-MIT
link or on Paper on SEAC or Whirlwind data acquisition
RC Matlack, The Role of Communication Networks in Digital Data
Systems, 1955 EJCC
Something by Licklider -- conceptual, stress on community of
users
Marill and Roberts, Toward a Cooperative Network of Timeshared
Computers, FJCC, 1966
Larry Roberts, Computer Resource Development to Achieve Resource
Sharing, 1970 SJCC
Roberts and Wessler, Computer Network Development to Achieve
Resource Sharing, 1970 SJCC
Ethernet paper
something by Paul Baran at RAND
7. Interpreted Languages
GOTRAN paper (Jack Palmer or Charles Davidson)
Dartmouth BASIC paper
Cliff Shaw, JOSS: A Designers View of an Experimental On-Line
System, 1964, FJCC
Dunn and Morrisy, Remote computing - An Experimental System,
1964 SJCC (several papers)
a paper on TINT at SDC
an article on Microsoft BASIC for the Altair
8. Component Technology
Ruth M. Davis, A History of Automated Displays, Datamation,
January, 1975
photo of mouse patent application
paper on first light pen
paper on the RAND tablet
paper on floppy disk (by Shugart?) from IBM
product announcement or photo or paper describing first low-
cost character-oriented terminal (whose was it?)
a Teletype photo
early microprocessor concept paper or a description of the
4004 (published or internal to Intel)
early speculation on the possibilities for IC memories and
logic (a widely read paper that stood in the same relationship
to IC technology as Strachey on timesharing or Licklider on
interactive applications)
discussion of early devices (research or product) from TI,
Fairchild, etc.
=====
Larry Press (lpress@venera.isi.edu)
10726 Esther Avenue, LA, CA 90064
(213) 475-6515andrew@jung.harlqn.uucp (Andrew Watson) (07/28/88)
You'll find copies of several seminal (good word, that) papers of relevance
in "Computer Structures: Principles & Examples", Siewiorek et al, McGraw-Hill
(all this from memory, so I may not have the title quite right). This
collection of reprints includes the Ethernet paper, the Alto paper and others
(including Wilkes' *original* microprogramming paper!), and is a happy hunting
ground for architectural archeologists like me.
On a more-or-less related note, the above-mentioned book contains plenty of
material on the PDP-8 and -11, but nothing on the DG Nova, which I'm told was
quite interesting, architecturally. Can anyone help me out with pointers to
information on this?
--
Regards,
Andrew.
+-----------------------------------------------------------------------------+
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+-----------------------------------------------------------------------------+rcorf@gecko.co.rmit.oz (Roy Ferguson) (08/04/88)
From article <ANDREW.88Jul28110736@jung.harlqn.uucp>, by andrew@jung.harlqn.uucp (Andrew Watson): > > You'll find copies of several seminal (good word, that) papers of relevance > in "Computer Structures: Principles & Examples", Siewiorek et al, McGraw-Hill > (all this from memory, so I may not have the title quite right). This > collection of reprints includes the Ethernet paper, the Alto paper and others > (including Wilkes' *original* microprogramming paper!), and is a happy hunting > ground for architectural archeologists like me. > > On a more-or-less related note, the above-mentioned book contains plenty of > material on the PDP-8 and -11, but nothing on the DG Nova, which I'm told was > quite interesting, architecturally. Can anyone help me out with pointers to > information on this? C. Gordon Bell, one of the authors of the original version of "Computer Structures ..." was associated with DEC. Now DEC do not appear to ever acknowledge the existence of DG as DG's founder, Edson DeCastro, was a former DEC engineer on the PDP-5 and PDP-8. In the book "Computer Engineering: A DEC view of hardware systems design" by Bell, Mudge & McNamara, Digital Press 1978, Edson DeCastro's name is mentioned just once. I think that explains why the Nova is not mentioned in "Computer Structures ...". Actually I have a copy of the first version of "Computer Structures ..." published in 1971 and that only has the PDP-8 and not the PDP-11. In fact the DG Nova was a 16-bit version of a 12-bit machine (the PDP-8) and architecturally is atrocious compared to the PDP-11 at least in my opinion. It has been a long time since I programmed a Nova, but it had only 4 registers and NO stack push or POP instructions. My memory is very rusty but I recall that interrupts always jumped to the location at address 0, there were 16 memory addresses in page 0 that were special, 8 were autoincrement and 8 autodecrement. It had the curious feature that on an indirect memory access if the high bit of the address was set it would treat that as another level of indirection and it would keep doing that until it found an address without the high bit set. Of course it could only address 16 bit words (NO byte addressing) so special coding was required to access a string of characters stored two to the word. Note that it still only had 32kword address space (allowing it to use the high bit for indirection as noted above). I suppose you could say it was interesting but you wouldn't want to program it in assembly language. Roy Ferguson, Dept. Communication & Electrical Eng., Royal Melbourne Institute of Technology.
mcdonald@uxe.cso.uiuc.edu (08/07/88)
>In fact the DG Nova was a 16-bit version of a 12-bit machine (the PDP-8) >and architecturally is atrocious compared to the PDP-11 at least in my >opinion. It has been a long time since I programmed a Nova, but it had >only 4 registers and NO stack push or POP instructions. >I suppose you could say it was interesting but you wouldn't want >to program it in assembly language. Actually, not very interesting to an old PDP-8 hand - but then not really so bad to program. Can you say "RISC"? There are several interesting anecdotes about this line. First, there was a thing called a "Supernova", which had semiconductor memory with a 300 nsec cycle time - this was 1971 or 1972. Second, DG had a really interesting construction technique - this was a Nova 1200. It had no case per se. There was a front panel and a power supply and a card cage. These things existed a separate objects, and bolted together to make the computer. Remove one for servicing and the whole thing fell to pieces. The power supply was one of the first switching mode supplies used in computers, and it had a horrible bug. There was no large capacitor on the output. It was supposed to depend on all those 0.01 microfarad things accross every IC. Well, the -5volt supply didnt power many IC's - it was just for the (analog) sense amps in the core memory. Problem was, it also powered the current loop in the ASR33 teletype, which used mechanical relays to generate output. This produced horrendous glitches on this line. If one occurred at the wrong point during a read cycle, the data got read correctly, but got put back in core wrong (for you newcomers, in core memories a read destroyed the contents of the cores,so every read had to be followed by a write). Unfortunately their diagnostics were so constructed that they could never, ever, catch this fault. The refused to admit it existed until I wrote a test which caught it within two or three keystrokes on the ASR33. A 50 cent electrolytic solved the problem. Doug McDonald
hwe@beta.lanl.gov (Skip Egdorf) (08/08/88)
In article <287@gecko.co.rmit.oz>, rcorf@gecko.co.rmit.oz (Roy Ferguson) writes: (regarding the DG Nova) > > I suppose you could say it was interesting but you wouldn't want > to program it in assembly language. > > Roy Ferguson, Dept. Communication & Electrical Eng., > Royal Melbourne Institute of Technology. On the contrary, the only way to program the Nova WAS in assembly language! A good one-sentence statement of difference between the Nova and the PDP-11 was that the regularity of the 11's instruction set made life easier for compilers, while the tricks in the Nova instruction set were better suited for the true assembly language wizard. A major reason that the 11 outsold the Nova was that this better fit where the computer industry went in the 1970s. Skip Egdorf hwe@lanl.gov
henry@utzoo.uucp (Henry Spencer) (08/08/88)
In article <46500024@uxe.cso.uiuc.edu> mcdonald@uxe.cso.uiuc.edu writes: >(for you newcomers, in core memories a read destroyed the contents of the >cores,so every read had to be followed by a write)... Dynamic RAMs are the same way, actually, although many people aren't aware of this because the chips hide most of the ugly details. It's one of the reasons why DRAM timing specs are sacrosanct and you take shortcuts at your peril. (Which means, for example, that if your CPU is in the habit of starting an access and then changing its mind, you have to be careful that the DRAM still sees a full legal access of some kind.) -- MSDOS is not dead, it just | Henry Spencer at U of Toronto Zoology smells that way. | uunet!attcan!utzoo!henry henry@zoo.toronto.edu
ward@cfa.harvard.EDU (Steve Ward) (08/10/88)
In article <1988Aug8.163944.29383@utzoo.uucp>, henry@utzoo.uucp (Henry Spencer) writes: > In article <46500024@uxe.cso.uiuc.edu> mcdonald@uxe.cso.uiuc.edu writes: > >(for you newcomers, in core memories a read destroyed the contents of the > >cores,so every read had to be followed by a write)... > > Dynamic RAMs are the same way, actually, although many people aren't aware > of this because the chips hide most of the ugly details. It's one of the > reasons why DRAM timing specs are sacrosanct and you take shortcuts at > your peril. (Which means, for example, that if your CPU is in the habit of > starting an access and then changing its mind, you have to be careful that > the DRAM still sees a full legal access of some kind.) > -- > MSDOS is not dead, it just | Henry Spencer at U of Toronto Zoology > smells that way. | uunet!attcan!utzoo!henry henry@zoo.toronto.edu actually, this is not correct. Magnetic cores operated with destructive readout, as claimed. This meant any read had to be coupled with a write-back cycle to retain the information. Dynamic RAM does not have destructive readout. In fact, the DRAM is refreshed with a read-only cycle in typical applications. DRAM's do have special timing and refresh considerations, though. A DRAM is made up of one or more circular, dynamic shift registers with read/write/address logic. As the bits circulate through the shift registers, the data decays. This is because the shift registers are analog and the data are electrical charges. This means that periodically the charges must be reamplified. The act of reading a DRAM will cause this reamplification, as will other methods (RAS-only access, for example). Reading does not destroy the data. The critical timing and special refresh considerations are related to the dynamic shift register nature of storage and access and the requirement to reamplify the shift register charges. I suppose one can construe destruction of a sort, in that in the act of reading, the stored charge feeds an amplifier which amplifies and restores a new charge into the shift register. This is really not a destructive readout, howeveer. The act of reading does not destroy the charge per-se, as it did in the magnetic cores. Certainly there is no DRAM write cycle automatically coupled with every DRAM read cycle, either, and I don't think the reference was to anything but a possible DRAM internal-only event, in any case. The exact internal goings-on are explained only at the block diagram level in data sheets, and this a recap of such an (old) data sheet as I understand it. <DON THE ASBESTOS CLOTHING :-) > fire away
fotland@hpihoah.HP.COM (Dave Fotland) (08/11/88)
/ hpihoah:comp.arch / ward@cfa.harvard.EDU (Steve Ward) / 3:41 pm Aug 9, 1988 / In article <1988Aug8.163944.29383@utzoo.uucp>, henry@utzoo.uucp (Henry Spencer) writes: >> >> Dynamic RAMs are the same way (destructive readout), although many >> people aren't aware >> of this because the chips hide most of the ugly details. >actually, this is not correct. >Dynamic RAM does not have destructive readout. In fact, the DRAM is >refreshed with a read-only cycle in typical applications. DRAM's do >have special timing and refresh considerations, though. >A DRAM is made up of one or more circular, dynamic shift registers with >read/write/address logic. As the bits circulate through the shift >registers, the data decays. This is because the shift registers are >analog and the data are electrical charges. This means that >periodically the charges must be reamplified. The act of reading a >DRAM will cause this reamplification, as will other methods (RAS-only >access, for example). >Reading does not destroy the data. The critical timing and special >refresh considerations are related to the dynamic shift register >nature of storage and access and the requirement to reamplify the >shift register charges. I can't believe he said this! DRAM's are not made out of shift registers! Internally, each bit is stored on a capacitor and it is lost during reading and is rewritten internal to the ram so you don't have to worry about it at the system level. There are zillions of papers and books on how DRAM's work if you are interested in more details.
scott@hpcvca.HP.COM (Scott Linn) (08/11/88)
/ hpcvca:comp.arch / ward@cfa.harvard.EDU (Steve Ward) / 3:41 pm Aug 9, 1988 / >Dynamic RAM does not have destructive readout. In fact, the DRAM is >refreshed with a read-only cycle in typical applications. DRAM's do >have special timing and refresh considerations, though. True. >A DRAM is made up of one or more circular, dynamic shift registers with >read/write/address logic. As the bits circulate through the shift >registers, the data decays. This is because the shift registers are >analog and the data are electrical charges. This means that >periodically the charges must be reamplified. The act of reading a >DRAM will cause this reamplification, as will other methods (RAS-only >access, for example). ><DON THE ASBESTOS CLOTHING :-) > >fire away ---------- DRAMS do refresh on read, but are not circular shift register arrays. Data is stored on a capacitor in a regular memory array (like a static ram), and the data eventually leaks off if not restored. The data is restored on read via a sense amp latch which feeds back to the memory cell and restores the correct level. I believe bubble memories consist of circular shift registers... Scott Linn HP - Northwest IC Division
rb@hpcuhb.HP.COM (Robert Brooks) (08/11/88)
> > A DRAM is made up of one or more circular, dynamic shift registers with > read/write/address logic. As the bits circulate through the shift > registers, the data decays. This is because the shift registers are > analog and the data are electrical charges. This means that > periodically the charges must be reamplified. The act of reading a > DRAM will cause this reamplification, as will other methods (RAS-only > access, for example). > > Reading does not destroy the data. The critical timing and special > refresh considerations are related to the dynamic shift register > nature of storage and access and the requirement to reamplify the > shift register charges. Where did you get this "shift register" business?? The storage mechanism of a DRAM is a charge stored on the gate of a FET. I believe a MOS capacitor (in addition to the inherent gate capacitance) is necessary to achieve the required capacitance, though this may not be the case in all designs. Reading would tend to be destructive of this charge via coupling through the FET, so a hidden, internal "write" is performed. Also, periodic refresh is needed due to leakage.
baum@Apple.COM (Allen J. Baum) (08/11/88)
[] >In article <46500024@uxe.cso.uiuc.edu> mcdonald@uxe.cso.uiuc.edu writes: >>In fact the DG Nova was a 16-bit version of a 12-bit machine (the PDP-8) >>and architecturally is atrocious compared to the PDP-11 at least in my >>opinion. I don't believe there is much resemblance between a PDP-8 and a Nova, even accounting for 16 vs. 12 bit words. The Nova was a Load/Store architecture, the first as far as I know. The rumors that go around are that it was designed at DEC to replace the PDP-8. The design was turned down, and the founders left DEC to form DG. The PDP-11 won the design contest, and came out a few years later. If you want to see a 16 bit version of the PDP-8, check out the HP-21xx series of computers. A direct ripoff, in almost every respect. -- {decwrl,hplabs,ihnp4}!nsc!apple!baum (408)973-3385
ward@cfa.harvard.EDU (Steve Ward) (08/11/88)
Well, DRAM's used to work that way 15 years ago! Seriously, for some reason (the devil made me do it) I was thinking of those old, very dynamic, CCD-style memory devices. The absence of a clock line on current DRAM's should make one suspicous as to its true nature. Present DRAM's utilize a static X-Y array of capacitors read via sense (comparator) amps. There is one capacitor for one bit. The capacitor charge is renewed during the read cycle. (isn't this a logical shift register of length 1? :-) ) The read cycle is clearly the place and time to do this since one has to know what to refresh. Back to the original topic, magnetic cores used a destructive readout method that inherently destroyed in absolute terms the stored information. This may be splitting hairs, but I don't think that this is the case with reading a capacitor charge via a comparator. Allright, maybe in practical terms the charge is emaciated to the point of unreliability without immediate refresh. Though I had the wrong device, my point was that the readout process wasn't inherently destructive in the way it is for magnetic cores. I still have my flame retardent undies on. :-) Here is one write-in response: -> Your understanding of DRAM operation is wrong, not even close. No, DRAMs never -> use shift registers for storage. You probably confused DRAMs with bubble -> memories or CCD RAMS. DRAMs are similar to SRAMs in that a 2D array of memory -> cells is addressed using x-y decoding. DRAMs store the data bits in capacitors -> instead of the latches used by SRAMs. Reading the capacitor state is -> destructive because most of the charge flows out to the sense line. Get your -> facts straight before you pose as an authority. I don't recall posing as anything, let alone an AUTHORITY. Does this mean most people just BELIEVE whatever I write? Hmm, posibilities...... :-) :-) Steven Ward ward@cfa
eugene@eos.UUCP (Eugene Miya) (08/11/88)
The book (proceedings) on The History of Personal Workstations, edited by
Adele Goldberg published by Addison-Wesley is now out. These are some
pretty old single user machines. Unfortunately, Alan Kay copped out and
reproduced the "Personal Dynamic Media" paper. The Alto papers
are good, and the LINC papers are not bad. Englebardt's talk can't
be captured by any paper. Get your company or school to buy this.
Another gross generalization from
--eugene miya, NASA Ames Research Center, eugene@aurora.arc.nasa.gov
resident cynic at the Rock of Ages Home for Retired Hackers:
"Mailers?! HA!", "If my mail does not reach you, please accept my apology."
{uunet,hplabs,ncar,decwrl,allegra,tektronix}!ames!aurora!eugene
"Send mail, avoid follow-ups. If enough, I'll summarize."tdonahue@bbn.com (Tim Donahue) (08/13/88)
In article <15355@apple.Apple.COM>, baum@Apple (Allen J. Baum) writes: >[] >>In article <46500024@uxe.cso.uiuc.edu> mcdonald@uxe.cso.uiuc.edu writes: >>>In fact the DG Nova was a 16-bit version of a 12-bit machine (the PDP-8) >>>and architecturally is atrocious compared to the PDP-11 at least in my >>>opinion. > >I don't believe there is much resemblance between a PDP-8 and a Nova, even >accounting for 16 vs. 12 bit words. The Nova was a Load/Store architecture, >the first as far as I know. ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Naaah. Check out the 16 bit Control Data 1700/1704/1774/1714/1784. Designed around 1964 (some say on the back of a napkin by this guy Cray), it had two registers (A and Q), one of which was really used for indexing. The first 1700 (with core) had a 1.1us cycle time; most instructions completed in one or two cycles. The 1784, using ICs, could be had in a 600ns version; the processor speed was limited by memory cycle times. These hardwired machines were designed for I/O intensive work, had buffered and unbuffered paths out of memory, were often connected to 3 Mb head-per-track disks, and blew the doors off PDP-11s (well, maybe not the mythical bipolar-memory 11/55). They still move hydrocarbons around at Exxon Bayway and Exxon Baytown, and jack the juice at REMVEC (RI, Eastern Mass, Vermont Energy Coop). What goes around comes around....Seymour's still 20 years ahead of everyone else. Except the Butterfly, of course! >{decwrl,hplabs,ihnp4}!nsc!apple!baum (408)973-3385 Cheers, Tim