mslater@cup.portal.com (Michael Z Slater) (10/20/89)
Alliant Computer and Intel announced a deal earlier this week, which involves a $3 million investment in Alliant from Intel, and the transfer from Alliant to Intel, for resale, of their parallelizing compilers. Another key part of the deal is the establishment of the PAX (parallel architecture extension), to become part of a multiprocessor binary standard for i860-based machines. Alliant has been building machines with hardware support for loop-level parallelism, and Intel will be building this technology into their next-generation i860 silicon. (Intel is evasive on whether the support will all be in the processor chip, or in support chips.) The PAX standard seems to involve lots of levels, including the API, the OS, the binary format, and scheduling and synchronization hardware. Essentially no details were provided in the announcement. Is anyone familiar with Alliant's loop-level parallelism scheme? Intel is pitching this as a major win for the i860, in that it gives them a binary standard for parallel computing, something no other processor has. Does anyone think this is really significant? Michael Slater, Microprocessor Report mslater@cup.portal.com 550 California Ave., Suite 320, Palo Alto CA 94306 415/494-2677 fax: 415/494-3718
lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay) (10/21/89)
In article <23184@cup.portal.com> mslater@cup.portal.com (Michael Z Slater) writes: >Alliant Computer and Intel announced a deal earlier this week... >Another key part of the deal is the establishment of the PAX (parallel >architecture extension), to become part of a multiprocessor binary standard >for i860-based machines. >Does anyone think this is really significant? That it's a standard? No. The Alliant compilers have to have some sort of spec for their output. When new, improved chips arrive, it's of course desirable that the spec not have to change. But if change was per-se horrible, then Intel wouldn't have so many instruction sets in its product line. What IS significant, is the technical direction that this signals. First, Alliant's compilers decide for themselves how to parallelize. The programmer doesn't have to provide compiler directives. Second, it means that Intel intends for us to build gangs of 860's. The Alliant scheme is based on the idea that typical code has nested loops, with each iteration of the inner loop, separable from the other iterations. So, there are N chunks of work, each chunk containing a single loop. Alliant runs the N chunks on M processors, M <= 8. When a processor finishes a chunk, it obtains another: there is an interprocessor bus for doling out the work. When all M processors are out of work, M-1 of them become irrelevant, and 1 of them continues forward through the serial program. Note that memory is an interesting issue in such systems. This is good stuff, but not unique. Cray has something similar called "microtasking". The Cray wrinkle is that a process on one CPU can have one ghost process on each of the other CPUs. When a CPU becomes idle, the OS checks to see if the CPU has any ghost processes, whose master processes (elsewhere) are now inside a nested loop. In this case, the OS fires up that ghost, which begins doing chunks of its master's work. Notice the neatness: the number of CPUs you get may actually fluctuate! -- Don D.C.Lindsay Carnegie Mellon Computer Science
brooks@vette.llnl.gov (Eugene Brooks) (10/21/89)
In article <23184@cup.portal.com> mslater@cup.portal.com (Michael Z Slater) writes: >Is anyone familiar with Alliant's loop-level parallelism scheme? >Intel is pitching this as a major win for the i860, in that it gives them >a binary standard for parallel computing, something no other processor has. >Does anyone think this is really significant? It may be a major "business win" for Intel, but the leading edge parallel code writers using the Alliant are NOT using their loop-level parallelism scheme. It does not support nested concurrency and routine level concurrency. You have to do that to be on the leading edge in parallel code performance. The techies won't care about this "pact" but the stock brokers might. brooks@maddog.llnl.gov, brooks@maddog.uucp
slackey@bbn.com (Stan Lackey) (11/14/89)
In article <36425@lll-winken.LLNL.GOV> brooks@maddog.llnl.gov (Eugene Brooks) writes: >In article <23184@cup.portal.com> mslater@cup.portal.com (Michael Z Slater) writes: >>Is anyone familiar with Alliant's loop-level parallelism scheme? >>Intel is pitching this as a major win for the i860, in that it gives them >>a binary standard for parallel computing, something no other processor has. >It may be a major "business win" for Intel, but the leading edge parallel >code writers using the Alliant are NOT using their loop-level parallelism >scheme. My take on this is that Intel may be considering only say a four processor system, where Alliant-style concurrency can work really well. It could be that Intel is thinking along the lines of a cache coherency scheme which only works on the bus-based model, which severely limits ther number of processors anyway. -Stan