baum@apple.UUCP (Allen J. Baum) (12/16/87)
-------- [] >In article <140@imagine.PAWL.RPI.EDU> beowulf!lunge!jesup@steinmetz.UUCP writes: >Given current technology, r2000 could probably be scaled to about 20 MHz. Note that the criticism of MIPs here is an implementation quibble. It appears to me to be a clever, well thought approach that appears to work with their current technology. Likewise, the 'slowness' of the SPARC architecture (2 cycle load/branches, etc.) are as well. They can, and I'm sure will, be fixed eventually if it becomes necessary- and object code will remain compatible, so no architectural tweaking is necessary. There are pipeline questions, especially involving Compare&Branch vs. Condition codes. One of the criticisms is that SPARC uses condition codes. There is also the criticism that, at the start of a branch, it is not known if the branch condition is met, and this adds a cycle to the branch. It seems to me that Compare&Branch would make this problem worse-- you're (in effect) delaying the condition setting operation until the branch, instead of performing it in the previous cycle. Separating the two, and letting the compiler schedule them even further apart (branch spreading is what ATT calls this technique in CRISP) gives more opportunity to 'know' which way the branch will go in time. -- {decwrl,hplabs,ihnp4}!nsc!apple!baum (408)973-3385