davidsen@crdos1.crd.ge.COM (Wm E Davidsen Jr) (11/18/89)
I was told several years ago that the Intel 8086 could support up to three coprocessors, because there was a two bit address field in the escape. Does this sound familiar to anyone? I looked in my 286 manual and didn't see it, but I can't put my hand on the original 8086 manual, or I might have just missed it. The person who told me this was a hardware hack, and described a system which used to 8087's and a custom multi-chip unit. The program wasn't funded, he left the company, and I saw something in another group about this. I thought Cray looked at multi-vector units per CPU and decided that they ate too much bandwidth, but a chip like the 8087 has a better ration of CPU time to memory bandwidth and could possibly get a big boost in performance. Yes I know the software would be messy. -- bill davidsen (davidsen@crdos1.crd.GE.COM -or- uunet!crdgw1!crdos1!davidsen) "The world is filled with fools. They blindly follow their so-called 'reason' in the face of the church and common sense. Any fool can see that the world is flat!" - anon
chip@vector.Dallas.TX.US (Chip Rosenthal) (11/18/89)
In article <1647@crdos1.crd.ge.COM> davidsen@crdos1.UUCP (bill davidsen) writes: > I was told several years ago that the Intel 8086 could support up to >three coprocessors, because there was a two bit address field in the >escape. Does this sound familiar to anyone? I don't believe this is quite it. I think it has to do with using the RQ/GTx lines for an external bus master. Quoth from the 8087 datasheet: The 8087 uses one of the request/grant lines of the 8086/8088 architecture (typically -RQ/-GT0) to obtain control of the local bus for data transfers. The other request/grant line is available for general system use (for instance by an I/O processor in LOCAL mode.) A bus master can also be connected to the 8087's -RQ/-GT1 line. In this configuration the 8087 will pass the request/grant handshake signals between the CPU and the attached master when the 8087 is not in control of the bus and will relinquish the bus to the master directly when the 8087 is in control. In this way two additional masters can be configured in an 8086/8088 system; one will share the 8086/8088 bus with the 8087 on a first-come first-served basis, and the second will be guaranteed to be higher in priority than the 8087. I think you might be misled by the 2-bit r/m field in the 8086/8 ESC (escape to external device) instruction. This field doesn't select the external device, but rather specifies the way to determine the effective address. When an ESC comes along, the 8086/8 just hangs out, hoping and waiting that there is something else out there which understands the instruction and can provide the result. It's very possible that somebody out there is using this multiple external bus master feature. But they probably ain't using it for the reason it was designed. Anybody out there remember the 8089 I/O coprocessor? Even more obscurely, is anybody out there using it? (Can you even buy one these days?) -- Chip Rosenthal / chip@vector.Dallas.TX.US / Dallas Semiconductor / 214-450-5337 Someday the whole country will be one vast "Metroplex" - Zippy's friend Griffy ===> addr changes 11/22 to "chip@chinacat.Lonestar.ORG" (texbell!chinacat!chip)