mark@hubcap.UUCP (Mark Smotherman) (12/06/88)
I would like to gather responses and corrections to an attempted taxonomy of
developments in I/O subsystems. I am particularly interested in program
sequencing as it relates to the control of I/O devices. If I can get an
accurate and complete list, I would like to send it somewhere like ACM
Comp. Arch. Newsletter. I will be glad to reference those who help me.
Please send your responses by email.
Following are I/O concepts and the machines in which they first appeared
(and also in which they were further developed). I can provide one or
more literature references for each machine, but there are probably many
references of which I'm not aware. I only have manuals for the IBM S/370
and XA.
synchronous transfer
--------------------
ERA 1103 (delivered 1953) - interlocked I/O; word at a time; a UNIVAC
1103A at NASA was the first to use the interrupt concept (1956, used to
preempt a batch machine to start collecting data from a wind tunnel)
IBM 702 (announced 1953) - CPU stalls while a block of characters are
transferred from an I/O device buffer; introduced control unit concept
asynchronous transfer with synchronous instruction to start transfer
--------------------------------------------------------------------
synchronization by interlock
----------------------------
UNIVAC I (1951) - one 60-word tape buffer each for input and output;
initial input instruction starts transfer to buffer and then releases
CPU for overlapped instruction execution; subsequent input instruction
dumps buffer to memory, starts next transfer, and then releases CPU;
if subsequent input instruction is issued too early then interlock
stalls CPU; I/O errors halt the CPU and operator must diagnose
synchronization by polling
--------------------------
* polling instruction either transfers word of block or alters program
sequence at completion
IBM 701 (announced 1952) - "copy logic": after an initial prepare to
read (or write) instruction, the program must issue a copy instruction
for each word in the transfer; a loop is coded to update the memory
addresses and issue the copies, and the loop may also perform
superficial processing such as character code conversion; the copy
instruction is interlocked so that an early issue is stalled until
the I/O device can provide/accept the next word; at end of file the
copy instruction causes a one-instruction skip, at the end of block
it causes a two-instruction skip
* polling to determine completion, separate instruction to transfer
(is there an earlier example than the PDP-8?)
* controller transfers words of block, polling to determine completion
(did Whirlwind I have this capability? -- Everett, 1951 paper: "In
general the computer continues to run during terminal equipment wait
times.")
IBM SAGE (started 1952, operational 1955) - I/O operations to start
block transfers of data to/from drum buffers; I/O operations proceed
in parallel with further CPU operations; a controller generates the
sequential memory addresses for the block and decrements a counter;
CPU has conditional branch to test completion of transfer; transfers
are interlocked so that CPU is stalled if second transfer is
attempted before previous one ends (Serrell, et al. in 1962 identify
"computation in parallel with I/O" as a significant new feature of
SAGE).
* I/O channel, polling to determine completion
IBM 709 (announced 1957) - I/O processor with specialized instruction
set; CPU has instruction to start channel and conditional branch to
test completion of channel function; start channel is interlocked so
that CPU is stalled if second start is issued before previous one ends
(note: Greenstadt paper says external interrupt available)
synchronization by interrupt
----------------------------
* interrupt to signal completion, separate instruction to transfer
NBS DYSEAC (2 papers published in 1954) - 2 program counters; I/O
signal causes CPU to switch PC's; bit in each instruction can force
switch back between PC's
Lincoln TX-2 (1957 paper) - "multiple sequence": 32 program counters;
each I/O device has a dedicated PC and operates at a fixed priority
(i.e. forerunner of interrupt vector); each instruction has break and
dismiss bits; break is used to indicate points at which a higher-
priority sequence can take over, while dismiss is used to allow lower-
priority sequences to resume
* controller transfers words of block, interrupt to signal completion
IBM 7070 (announced 1958) - "priority processing" (I/O interrupt);
I/O completion causes CPU to switch to uninterruptible priority
routine; return address stored in register; scatter/gather capability
possible with chain of record definition words (note: Bell & Newell
would classify this as a Pio since they see the chain as essentially
a series of jump instructions)
IBM STRETCH (started 1954, delivered 1961) - I/O exchange acts as
byte multiplexor; I/O completion is part of a comprehensive interrupt
vector facility (vector contains single instructions to be executed
outside the normal instruction cycle, these instructions can be single-
instruction fixups or subroutine calls); interrupt nesting allowed
* I/O channel, interrupt to signal completion
IBM 7090 (announced 1958) - addition of data-channel trap (I/O
interrupt) to 709 architecture; causes CPU to branch to special
instruction sequence
* I/O processor, interrupt to signal completion
UNIVAC LARC (started 1954, delivered 1960) - high-level request
packets (e.g. record number or key) are sent to an I/O processor,
which also performs services such as device queueing; the requesting
processor is interrupted when its request is complete; main memory
contention is resolved by a time-slotted memory bus
asynchronous transfer with IOP polling to start transfer
--------------------------------------------------------
CDC 6600 (1964) - in the typical OS structure, PPUs poll reserved main
memory locations (input mailboxes) to determine I/O requests; after
starting a device in response to an I/O request, a PPU will poll the
device until completion; at completion the PPU will place a completion
notice in its output mailbox; programs can poll the output mailbox or
can be suspended until the PPU running the OS sees the completion notice
and resumes the program by an exchange jump; before an output transfer
the PPU must move the data from the shared main memory to its local
memory, likewise after an input transfer the PPU must move the data from
its local memory to the shared main memory; PPU execution is time-shared
equally
TI-ASC - PPU execution can be weighted to favor certain PPU's
asynchronous transfer with IOP queueing to start transfer
---------------------------------------------------------
Burroughs B7700 (1973) - reserved locations exist in main memory that define
head and tail pointers to I/O device request queues and I/O completion block
queues; queue manipulations by the CPU and I/O processors are atomic actions;
any IOP can handle any device; a start I/O instruction begins IOP processing
on a specified device queue; processing continues until an error, interrupt,
or empty queue; the CPU polls the completion block queue; optionally
interrupts can be generated on completion of each request
Honeywell Series 60 Level 64 (1974) - microcoded semaphore operations used
in I/O
asynchronous transfer with asynchronous instruction to start transfer
---------------------------------------------------------------------
IBM S/370 (1970) - SIOF (start I/O fast release) used to release CPU
after channel has fetched CAW and before the channel has determined if
I/O operation can be successfully initiated; interrupt occurs if device
or path is busy (was assumed to be infrequent but on later systems the
interrupt overhead canceled out performance gain from early release of CPU)
multiprocessor I/O with polling
-------------------------------
Plessey System 250 (1969) - memory-mapped I/O with capability protection;
device drivers get requests from memory queues and poll until transfer is
complete; interrupt-like system is also available in which each processor
periodically (i.e. 100 microsec.) examines a common status word for
interrupt requests (various papers differ on its use in I/O)
multiprocessor I/O with asymmetric interrupts
---------------------------------------------
Burroughs B5500 (1964) - only master processor can initiate I/O; ITI
instruction to test for pending interrupt at end of interrupt handling
multiprocessor I/O with symmetric interrupts
--------------------------------------------
Burroughs B-825 (1962) - all interrupts are transmitted to each processor;
different masks in the processors determine which one will respond to a
given interrupt
IBM S/370 XA (1983) - subchannel per device; any CPU can start I/O on any
device and any CPU can accept an interrupt; path busy queueing handled by
channel subsystem; test pending interruption instruction to avoid immediate
context switch after LPSW
Sequent Balance (1986) - SLIC interrupts processor with least priority
I would like to start a collection of papers, relevant manual sections, and
example I/O code for the above machines. If you have pointers to sources of
this kind of information, I would certainly like to hear about it. (If
you recommend writing to a manufacturer, can you identify specific persons
or groups? This is especially important since most of these machines are 20-
40 years old.)
Also, are there interesting/important machines that are left out of the
chronology? Would you please identify them along with literature references?
How about concepts? Does the above list contain all the important concepts?
--
Mark Smotherman, Comp. Sci. Dept., Clemson University, Clemson, SC 29634
INTERNET: mark@hubcap.clemson.edu UUCP: gatech!hubcap!mark