mmm@cup.portal.com (Mark Robert Thorson) (04/08/90)
Will there ever come a time when more than two portions of the address are strobed into the multiplexed address pins of DRAM's? For example, will there be something like a page address, in addition to row and column? Does anyone already do this? Or will it make more sense to multiplex address and data, sending in perhaps a 32- or 64-bit physical address, then reading data on the same pins? This would be the most efficient use of pins if the host processor always bursts its reads and writes, and the DRAM can send a new consecutive data item on every clock. Or will a more clever configuration be used? Also, will pseudostatic DRAM's eventually win? I notice the Hitachi PRAM's are just as dense as their DRAM's (4Mb). I suppose this means that the extra logic required to get the maximum user-friendly refresh mechanism is now a tiny % when compared to the size of the memory planes. Or, will SRAM's eventually surpass DRAM's in density? I've heard this comparison: how small can you make a capacitor / how small can you make six transistors. Will transistors eventually become so small that six interconnected transistors together are smaller than a minimum-size capacitor. Or will the capacitors scale down as far as transistors can go? (Please indicate year if you think one technology will prevail first, then another will take over. If two technologies co-exist, I want to know which one will be used for high-end personal computers. State whether you're assuming a "personal computer" is desktop, laptop, brain implant, etc.)
johne@hpvcfs1.HP.COM (John Eaton) (04/10/90)
<<<<
< Also, will pseudostatic DRAM's eventually win? I notice the Hitachi PRAM's
< are just as dense as their DRAM's (4Mb). I suppose this means that the extra
< logic required to get the maximum user-friendly refresh mechanism is now
< a tiny % when compared to the size of the memory planes.
----------
Pseudostatics really don't compete directly with normal DRAM's. A good rule
of thumb is if your memory needs will fit in eight or fewer IC's then use
pseudo's otherwise use normal DRAMS. For large systems the lower pin count
of normal drams means lower parts cost and fewer traces that offsets the
extra cost of the address mutliplexor.
John Eaton
!hpvcfs1!johne
patel@uicsgva.csg.uiuc.edu (04/10/90)
I am not a VLSI or Memory Expert but some of this information you
can find in literature on memory. Most likely, this note is not being
read by RAM designers, so I thought I should clear up the picture on
RAM.
DRAMs:
Present day DRAMs use a 3-D capacitor, called Trench Capacitor.
A Trench Capacitor has a small footprint on chip but effectively
gives you a larger surface area. By contrast a 2-D (planar)
capacitor has an effective area equal to its footprint.
From Physics/EE 101 everyone should recall that the capacitance is
proposrtional to the area of the parallel plates.
2-D Capacitor Trench Capacitor
---~~~~~--- --- ---
---~~~~~--- --\\ //--
\\_//
\_/
So the trecnch capacitor has a capacitance larger than an
equal-footprint planar capacitor. You need a large capacitor
1. To hold the data for reasonable time before you need a refresh.
Charge retention depends heavily on your process, how good is your
manufacturing process to hold the leakage currents to a minimum etc.
2. To tell the difference between charge (1) and no-charge(0)!
In fact this is a very serious problem. Unlike ordinary logic
levels, (0 for < 1 volt and 1 for > 2.5 volts) you have to sense
very small voltage swings between a logic 0 and 1. To sense the
presence of an extremely small charge against various odds
(noise, leakage, long wires, temperature variations etc.) is
no small feat. Design of sense amps is considered a
black art.
SRAMs:
Static RAM cell does not need a capacitor to work.
Static RAMs canont be scaled down arbitrarily for the same reason
as DRAM can't. The same problem exists with small transitors
as with small capacitors, namely, driving long lines and
reliably differentiating between 1 and 0 at the sense amp.
-J. Patel
Univ. of Illinois, Urbana-Champaign
patel@csg.uiuc.edu