rb@vlsi.cs.cmu.edu (Roberto Bisiani) (05/07/87)
Keywords:
The 14th Annual
INTERNATIONAL SYMPOSIUM ON
COMPUTER ARCHITECTURE
Sheraton - Station Square
Pittsburgh, PA USA
June 2 - 5, 1987
ADVANCE PROGRAM
TUESDAY - JUNE 2, 1987
Tutorials
10:00-6:00 Microprocessor Logic Design: The Flowchart Method
N. Tredennick, Nexgen, Sunnyvale, CA
or
Highly Parallel Systolic Arrays: Theory, Implementation
and Applications
H. T. Kung, CMU, Computer Science Department
WEDNESDAY - JUNE 3, 1987
8:00 Conference Registration
9:00 Branching Techniques
Chair: Alan Smith, Univ of California, Berkeley
Branch Folding in the CRISP Microprocessor:
Reducing Branch Delay to Zero
D. R. Ditzel, H. R. McLellan, AT&T Bell
Laboratories, Murray Hill, NJ
An Evaluation of Branch Architecture
Henry M. Levy, Univ. of Washington, Seattle, WA
10:00 BREAK
10:30 Pipelining
Chair: Edward S. Davidson, Univ. of Illinois at Urbana-Champagne
Checkpoint Repair for Out-of-Order Execution Machines
Yale Patt, Univ. of California, Berkeley
Instruction Issue Logic for High Performance Interruptable
Pipeline Processors
Gurindar S. Sohi, Sriram Vajapeyam, Univ. of Wisconsin
Fast Temporary Storage for Serial and Parallel Execution
John Swensen, Yale Patt, Univ. of California, Berkeley
12:00 LUNCH
12:45 Conference Welcome - Dr. Zary Segall, Chairman
1:00 Keynote Address - Dr. Raj Reddy
2:00 Special Purpose Hardware
Chair: H. T. Kung, CMU
Performance Analysis & Design of a Logic Simulation
Machine
Ken Wong and Mark A. Franklin
Univ. of Washington, St. Louis, MO
A Modular Systolic Architecture for Image
Convolutions
Kshitij Doshi and Peter Varman
Rice University, Houston, TX
A Template Matching Algorithm Using
Optically-Connected 3D-VLSI Architecture
Satoshi Fujita, Reiji Aibara, Masafuni Yamashita,
and Tadashi Ae
Hiroshima University, Japan
Data Flow
Chair: (to be announced)
Mapping Data Flow Programs on a VLSI Array of
Processors
Bilha Mendelson and Gabriel M. Silberman
Technion-Israel Inst. of Technology, Haifa, Israel
Analytical Modeling and Architectural Modications
of a Dataflow Computer
D. Ghosal and L. N. Bhuayn
Univ. of Southwestern Louisiana, Lafayette, LA
A Unified Resource Management and Execution Control
Mechanism for Data Flow Machines
Masaru Takesue
N.T.T. Electrical Communications Lab, Tokyo, Japan
3:30 BREAK
4:00 Panels
A. Are General Purpose Systolic Architectures
for Real?
B. The Future of Data Flow
5:30-7:00 RECEPTION
SIGARCH Meeting
THURSDAY - JUNE 4, 1987
8:30 Prolog
Chair: Douglas Degroot, Xenologic
High Performance Integrated Prolog
Processor IPP
S. Abe, T. Bandoh, S. Yamaguchi, K. Kurosawa,
K. Kiriyama
Hitachi Research Laboratory, Hitachi Ltd.,
Tokyo, Japan
Performance Studies of a Parallel Prolog Architecture
Barry S. Fagin and A. M. Despain
Univ. of California, Berkeley, CA
An Experimental VLSI PROLOG Interpreter:
Preliminary Measurements and Results
P. L. Civera
Politecnico de Torina, Italy
Interconnection Networks
Chair: Harold S. Stone, IBM T.J. Watson Research Center
Rearrangeability of Multistage Prolog Machine IPM
A. Varma
IBM T. J. Watson Research Center, Yorktown, NY
Optimized Mesh-Connected Networks for SIMD
and MIMD
R. Beivide, E. Herrada, J. L. Balcazar, and J. Labarta
Universidad Politecnica de Cataluna, Barcelona, Spain
Performance Evaluation of Reduced Bandwidth Multistage
Interconnection Networks
D. T. Harper III and J. R. Jump
Rice University, Houston, TX
10:00 BREAK
10:30 Symbolic Architectures
Chair: Alvin M. Despain, Univ. of California, Berkeley
Deterministic and Stochastic Modeling of
Parallel Garbage Collection - Towards Real-Time
Criteria
Oliver Ridoux
IRISA/NRIA, Rennes, France
The Sharing of Environment in and/or Parallel
Execution of Logic Programs
Sun Chengzheng, Tzu Yungui
Changsha Institute of Technology, China
Architectural Issues in Designing Symbolic Processors
in Optics
Aloke Guha and Raja Ramnarayan - Honeywell, Inc.,
Golden Valley, MN
Matthew Derstine - Honeywell, Inc., Bloomington, MN
Interprocessor Communications and Synchronization
Chair: Michel Dubois, Univ. of Southern California
Hardware Support for Interprocess Communication
Umakishor Ramachandran - Georgia Institute of
Technology
Marvin Solomon and Mary Vernon - Univ. of Wisconsin,
Madison, WI
Architecture of a Message-Driven Processor
William J. Dally
M.I.T., Cambridge, MA
Effect of Storage Allocation/Reclamation Methods on
Parallelism and Storage Requirements
Manoj Kumar
IBM T. J. Watson Research Center, Yorktown Heights,
NY
12:00 LUNCH
12:45 Eckert-Mauchley Award
1:00 Featured Presentation
C. Gordon Bell
National Science Foundation
2:00 Memory Systems
Chair: John Shen, CMU
Cache Design of a Sub-Micron CMOS System/370
J. H. Chang, H. Chao, and J. Tang
IBM T. J. Watson Research Center
Yorktown Heights, NY
An Architectural Perspective on a Memory Access
Controller
Martin Freeman
Stanford University, Stanford, CA
Organization and Analysis of a Gracefully-Degrading
Interleaved Memory System
Kifung Cheung, Gurinda Sohi, and Kewal Daluja
University of Wisconsin, Madison, WI
3:30 BREAK
4:00 Cache Design
Chair: Thomas Eggers, Digital Equipment Corp.
Correct Memory Operation of Cache Based
Multiprocessors
Michel Dubois
University of Southern California, Los Angeles, CA
Hierarchical Cache/Bus Architecture for Shared
Memory Multiprocessor
Andrew W. Wilson
Encore Computer Corp., Marlboro, MA
Multiprocessor Cache Design Considerations
Roland L. Lee, Pen-Chung Yew, and Duncan H. Lawrie
University of Illinois, Urbana, IL
FRIDAY - JUNE 5, 1987
8:30 Register-Memory Hierarchy
Chair: David Patterson, Univ. of California-Berkeley
Performance Evaluation of Multiple Register Sets
Richard Eickemeyer and Janak H. Patel
University of Illinois, Urbana, IL
A Performance Analysis of Automatically Managed Top
of Stack Buffers
Timothy J. Stanley, Digital Equipment Corp.
Robert G. Wedig, Wedig Consulting Services
Palo Alto, CA
Tradeoffs in Vector Architecture
Brian Moore, Andris Padegs, Ron Smith,
Werner Buchholz
Data Systems Div., IBM Corporation
Poughkeepsie, NY
10:00 BREAK
10:30 Processor Architectures
Chair: John Hennessy, Stanford University
WISQ: A Restartable Architecture Using Queues
A. R. Pleszkun, J. R. Goodman, W-C. Hsu, R. T. Joersz,
G. Bier, P. Woest, P. B. Schechter
University of Wisconsin, Madison, WI
Architectural Tradeoffs in the Design of MIPS-X
Paul Chow and Mark Horowitz
Jet Propulsion Laboratory, Pasadena, CA
The Hardware Architecture of the CRISP Microprocessor
A. D. Berenbaum, D. R. Ditzel, and H. R. McLellan
AT&T Bell Laboratories, Murray Hill, NJ
12:00 ADJOURN
2:00 Visit and Demo at CMU
-------TURORIAL INFORMATION-------
Microprocessor Logic Design: The Flowchart Method
Abstract: This tutorial will cover the logic design method used to design
the Motorola MC68000 series and the IBM Micro/370 microprocessors. The
"flowchart method" is an industrial logic design method for designing single
chip microprocessors. The internal workings of a microprocessor will be
covered and specific examples from the IBM Micro/370 and Motorola MC68000
designs will be given.
Speaker: Nick Tredennick, currently the Director of Product
Development at Nexgen Microsystems, designed the CPU logic and microcode
for the Motorola MC68000 microprocessor and for the IBM Micro/370
microprocessor. He is the author of the forthcoming book "Microprocessor
Logic Design: The Flowchart Method" (Digital Press).
Highly Parallel Systolic Arrays: Theory, Implementation and
Applications
Abstract: This tutorial will cover advances in the theory and
implementation of systolic arrays in applications areas including signal
processing, computer vision and non-numeric algorithms. Examples will be
drawn from work performed at Carnegie Mellon and elsewhere, incuding
collaborative efforts with General Electric and Intel.
Speaker: H. T. Kung is Professor of Computer Science at Carnegie
Mellon University. He is the originator of the systolic array approach
to parallel computation, and currently leads several parallel
supercomputer implementation projects.
-------REGISTRATION-------
Conference registration includes lunches, a copy of the proceedings, and a
reception. The student fee does not include the reception. Tutorial
registration includes notes, coffee breaks, and lunch. Registration for
the tutorials is limited, and will be allotted on a first-come basis.
Preregistration for the tutorials is required.
-------LOCATION-------
Both the Sheraton Hotel at Station Square and the Westin William Penn are
located in Downtown Pittsburgh, about half an hour from the Pittsburgh
Airport. There is a direct bus service between the airport and the two
hotels. Busses leave every half hour. Parking is available at both
hotels.
Make checks payable to 1987 Computer Architecture Symposium (U.S.
currency only) and, supplying the proper information, mail to:
1987 Computer Architecture Symposium
P. O. Box 14
Carnegie Mellon
Pittsburgh, PA 15213
Conference Fees: Advance* On Site
Member ____$150 ____$180
Non Member ____$185 ____$225
Student ____$ 30 ____$ 40
Tutorial Fees:
Member ____$125 ____$150
Non Member ____$160 ____$190
Student ____$ 25 ____$ 40
*Must be received by May 18, 1987
Name__________________________________________________________________________
Affiliation___________________________________________________________________
Address_______________________________________________________________________
City_____________________________________________State__________Zip___________
Country__________________________________________Phone________________________
IEEE Member No.__________________________________
Amount Enclosed__________________________________
HOTEL RESERVATION
June 1 - 5, 1987
Please mail required information before May 19, 1987 to:
The Sheraton Hotel at Station Square
7 Station Square Drive
Pittsburgh, PA 15219
(412) 261-2000
Single____$80 Double____$90
--or--
Please mail required information before May 7, 1987 to:
Westin William Penn Hotel
530 William Penn Way
Pittsburgh, PA 15230
(412)553-5100
Single____$90 Double____$110
Name__________________________________________________________________________
Address_______________________________________________________________________
City____________________________________________State___________Zip___________
Country_________________________________________
Arrival Date________________________Hour________
Departure Date______________________