lindsay@K.GP.CS.CMU.EDU (Donald Lindsay) (01/23/88)
In article <1071@cpocd2.UUCP> howard@cpocd2.UUCP (Howard A. Landman) writes: >If anyone sees a photo of the chip, here's an easy way to tell RISC from CISC: >Identify the datapath and RAM (including register file and cache). If they >add up to less than half the chip area, it's a CISC. That's because the rest >is probably all control, and any chip that's more than half control does not >have a simple architecture. Some recent chips seem to put more real estate into bonding pads and pin drivers, than into anything else. I assume that the power consumption is there, too. -- Don lindsay@k.gp.cs.cmu.edu CMU Computer Science
howard@cpocd2.UUCP (Howard A. Landman) (01/29/88)
In article <1071@cpocd2.UUCP> howard@cpocd2.UUCP (Howard A. Landman) writes: >If anyone sees a photo of the chip, here's an easy way to tell RISC from CISC: >Identify the datapath and RAM (including register file and cache). If they >add up to less than half the chip area, it's a CISC. That's because the rest >is probably all control, and any chip that's more than half control does not >have a simple architecture. In article <701@PT.CS.CMU.EDU> lindsay@K.GP.CS.CMU.EDU (Donald Lindsay) writes: >Some recent chips seem to put more real estate into bonding pads and pin >drivers, than into anything else. I assume that the power consumption is >there, too. As linewidths shrink, pads do not, so they do consume a lot of nanoacreage. This was so obvious to me that I didn't even think to mention it. To be accurate, I should have said "the chip core area (excluding pads)", not "the chip area". Sorry if anyone got confused. As I've pointed out in another posting, this was meant to be a quick rule of thumb for guessing, not a definition of RISC or CISC. -- Howard A. Landman {oliveb,hplabs}!intelca!mipos3!cpocd2!howard howard%cpocd2.intel.com@RELAY.CS.NET "... all the words float in sequence. No one knows what they mean, ..."