zs01+@andrew.cmu.edu (Zalman Stern) (07/14/89)
> Excerpts from ext.nn.comp.arch: 10-Jul-89 Re: Compiling - RISC vs. CISC > Robert Cousins@dg.dg.com (1876) [text deleted] > At one point, people were talking about RISC processors > needing to execute MORE instructions to do the same amount of work. > THis implied that where a CISC might require 100 instructions, a > RISC might require >100 instructions, though the RISC instructions > would take less time. We have noticed that in many cases, the > instruction count goes down. In fact, the best example is the > Dhrystone benchmark. Since Dhrystone is an artificial measure of > integer compute power, a "Dhrystone MIPS" is considered one VAX MIPS > of compute power. On the 88K, we need less than 1 MIPS to generate > a Dhrystone MIPS. In other words, we get Dhrystone MIPS > CPU > clock speed. When this first happened here, many people were > mumbling about clocks running backward and Escher paintings . . . . :-) > Excerpts from ext.nn.comp.arch: 13-Jul-89 Re: Compiling - RISC vs. CISC > Robert Cousins@dg.dg.com (1858) > Hugh, I agree that Dhrystone is one benchmark in a whole field of > benchmarks. However, I feel comfortable drawing a simple conclusion > from this result: It is not clear that a CISC processor will take > FEWER INSTRUCTIONS to solve a problem than a RISC processor. In some > cases RISCs may require fewer instructions. [text deleted] > Robert Cousins > Dept. Mgr, Workstation Dev't. > Data General Corp. The situation given in the first excerpt is in no way supporting data for the conclusion made in the second excerpt. In order for the first to be at all surprising, one must assume that "Dhrystone MIPS" are related to native instruction issue rate. This is not true. To make the discussion clearer, I will introduce some notation: DPS(machine) = Dhrystones Per Second for machine. NIIR(machine) = Native Instruction Issue Rate of machine, VUP(machine) = VAX Unit of Performance measure for machine. (For the sake of this argument, a VAX 11/780 is one VUP.) I use VUP here because MIPS is often confused with native instruction issue rate. This is very seldom what is meant by MIPS. Therefore, I will avoid the term MIPS entirely. An 11/780 gets something like 1700 Dhrystones. Hence there are about 1700 Dhrystones to the VUP. As far as I can tell, Robert Cousins statement was that he was surprised by the fact that for their 88k machine, the following was true: (DPS(88k) / 1700) > NIIR(88k) I take it that Robert was surprised by this because he supposed: *) (DPS(VAX 11/780) / 1700) = NIIR(11/780) Substituting the values of DPS(88k) that he was getting, NIIR(88k) turned out greater than the clockspeed of the 88k machine. His conclusion was that the 88k was executing less instructions than the VAX. It has been covered before in comp.arch that a VAX 11/780 really has a native instruction issue rate of somewhere in the neighborhood of 500k instructions per second. This makes the *'ed equation untrue. This is the fallacy in the above conclusion. In fact, making any native instruction issue rate conclusions based on Dhrystones is a bad idea since it is doubtful that the two machines are executing anything close to the same code. Another problem here is that the term RISC is as bogus as the above usage of the MIPS abbreviation. The 88k differs from other processors described as RISC in that it has addressing modes for its load and store instructions. There are probably interesting discussion to be had as to code density and architectural features (i.e. address modes), but I don't have any data so I'll shut up. Sincerely, Zalman Stern Internet: zs01+@andrew.cmu.edu Usenet: I'm soooo confused... Information Technology Center, Carnegie Mellon, Pittsburgh, PA 15213-3890
rec@dg.dg.com (Robert Cousins) (07/14/89)
In article <EYjByca00Vs8ILNl8K@andrew.cmu.edu> zs01+@andrew.cmu.edu (Zalman Stern) writes: >> I wrote: >> Hugh, I agree that Dhrystone is one benchmark in a whole field of >> benchmarks. However, I feel comfortable drawing a simple conclusion >> from this result: It is not clear that a CISC processor will take >> FEWER INSTRUCTIONS to solve a problem than a RISC processor. In some >> cases RISCs may require fewer instructions. > [text deleted] > >As far as I can tell, Robert Cousins statement was that he was surprised >by the fact that for their 88k machine, . . . . > I apparently did not make my point clear. Let me try it again: There has been a somewhat widespread use do the term "Dhrystone MIPS" in the industry. This is commonly linked to some actual measure of performance. There has been fast and loose use of this term interchangeably with the other relatively useless measure of performance MIPS. Not only are these two measures not the same but they are only of limited applicability. The example I gave earlier where Dhrystone MIPS > Raw MIPS disproves the similarity. On a slightly different front, I think this inequality can be used as anecdotal evidence that perhaps the traditional belief that the # CISC instructions < # RISC instructions to do the same job does not always hold true. >Another problem here is that the term RISC is as bogus as the above >usage of the MIPS abbreviation. The 88k differs from other processors >described as RISC in that it has addressing modes for its load and store ^^^^^^^^^^^^^^^^ >instructions. There are probably interesting discussion to be had as to >code density and architectural features (i.e. address modes), but I >don't have any data so I'll shut up. > >Sincerely, >Zalman Stern >Internet: zs01+@andrew.cmu.edu Usenet: I'm soooo confused... >Information Technology Center, Carnegie Mellon, Pittsburgh, PA 15213-3890 The addressing modes for the 88100 loads and stores are: Immediate Register Indirect with immediate index Register Indirect with index Register Indirect with scaled index In the immediate form, a 10 or 16 bit (depending upon the instruction) value is used as an operand. In the Register Indirect with Immediate form, a 16 bit unsigned (yes, unsigned) value is added to the contents of the register to form the address. In the Register Indirect with Index form, two registers are added together to form the effective address. In the Register Indirect with Scaled Index form, two registers are added together after one is shifted left 0 to 3 bits. All load instructions take the same amount of time and are all 4 bytes long. If this makes the 88K non-RISC, then I must ask you to produce a true RISC machine for reference which has no non-RISC features. Robert Cousins Dept. Mgr, Workstation Dev't. Data General Corp. Speaking for myself alone.
hawkes@mips.COM (John Hawkes) (07/16/89)
In article <201@dg.dg.com> uunet!dg!rec (Robert Cousins) writes: >I apparently did not make my point clear. Let me try it again: > > There has been a somewhat widespread use do the term > "Dhrystone MIPS" in the industry. This is commonly > linked to some actual measure of performance. There > has been fast and loose use of this term interchangeably > with the other relatively useless measure of performance > MIPS. Not only are these two measures not the same but > they are only of limited applicability. The example I > gave earlier where Dhrystone MIPS > Raw MIPS disproves > the similarity. I still think you're misunderstanding. "Dhrystone MIPS" have nothing whatsoever to do with "Raw MIPS". I define "Raw MIPS" to be the number of millions of native instructions per second that a system executes for a given application. This value might be interesting in some quarters, but it's generally useless in comparing different architectures. If we assume that by "MIPS" you mean "VUPS", or some value relative to a VAX/780 (running some specified compilers and OS), then the term "Dhrystone MIPS" (or "Dhrystone VUPS") was coined as a caveat to explain how a particular system's MIPS "rating" was computed. You can choose a spectrum of benchmarks and compute some kind of reasonable mean performance value, or you can pick one benchmark which shows the highest value, albeit an unrepresentative one. Dhrystone is one such benchmark. This is like an auto manufacturer claiming a miles-per-gallon rating based upon 45 MPH steady highway driving. Fine, but don't try to compare this value with everyone else's values which are computed differently. "Dhrystone MIPS" is to "MIPS" (=="VUPS") as "Highway Mileage" is to "Mileage". And none of these things has anything to do with "Raw MIPS". -- John Hawkes {ames,decwrl}!mips!hawkes OR hawkes@mips.com
ray@dsiramd.dsir.govt.nz (Ray Brownrigg) (07/18/89)
In article <23375@sprint.mips.COM> hawkes@mips.COM (John Hawkes) writes: > "Dhrystone MIPS" have nothing >whatsoever to do with "Raw MIPS". I define "Raw MIPS" to be the number of >millions of native instructions per second that a system executes for a given >application. However "Dhrystone MIPS" still has not been accurately defined. Dhrystone MIPS is a shorthand term for "(Dhrystones per second)/1757" where 1757 is the 'current' value (i.e. whatever value the author choses to use) for Dhrystones/sec on a VAX/780. Thus the term means the speed (relative to a VAX/780) of executing the Dhrystone benchmark. Note that the Dhrystone benchmark measures "*Dhrystone instructions* per second", and so in fact a VAX/780 runs at ~0.00175 million Dhrystone instructions per second, or .00175 Dhrystone Mips if you care to look at it that way! Of course a single Dhrystone 'instruction' has nothing at all to do with the architecture of a CPU, it is a concept designed purely for benchmarking purposes. -- Ray Brownrigg domain: ray@dsiramd.dsir.govt.nz Applied Maths Div, DSIR ACSnet: ray@dsiramd.nz[@munnari] PO Box 1335 System: OLIVETTI/AT&T 3B2/400B+, System V R3.0 Wellington, New Zealand "unx -rul
bhoward@inquiry.org (Bruce Howard) (07/19/89)
In article <23375@sprint.mips.COM> hawkes@mips.COM (John Hawkes) writes: >If we assume that by "MIPS" you mean "VUPS", or some value relative to a >VAX/780 (running some specified compilers and OS), then the term "Dhrystone >MIPS" (or "Dhrystone VUPS") was coined as a caveat to explain how a particular >system's MIPS "rating" was computed. You can choose a spectrum of benchmarks >and compute some kind of reasonable mean performance value, or you can pick >one benchmark which shows the highest value, albeit an unrepresentative one. >Dhrystone is one such benchmark. This is like an auto manufacturer claiming >a miles-per-gallon rating based upon 45 MPH steady highway driving. Fine, but >don't try to compare this value with everyone else's values which are computed >differently. "Dhrystone MIPS" is to "MIPS" (=="VUPS") as "Highway Mileage" >is to "Mileage". And none of these things has anything to do with "Raw MIPS". i like the term mups (mythical units of processing) coined by peter honeyman. bruce
frank@zen.co.uk (Frank Wales) (07/25/89)
In article <1989Jul18.220621.8941@inquiry.org> bhoward@inquiry.org (Bruce Howard) writes: >i like the term mups (mythical units of processing) coined by >peter honeyman. Or where MIPS == Meaningless Indicator of Processor Speed. -- Frank Wales, Systems Manager, [frank@zen.co.uk<->mcvax!zen.co.uk!frank] Zengrange Ltd., Greenfield Rd., Leeds, ENGLAND, LS9 8DB. (+44) 532 489048 x217