gsg0384@uxa.cso.uiuc.edu (06/08/90)
Hi, Do you have any benchmark figures for MIPS 6000 cpu and the 6010 fpu? I was told that the new machine from DEC will be based on these chips, and that Bull has already announced a machine with this chip. Any more information on these new machines? Price information is also wanted. Thanks a lot for the information.
cprice@mips.COM (Charlie Price) (06/09/90)
In article <47100002@uxa.cso.uiuc.edu> gsg0384@uxa.cso.uiuc.edu writes: > >Hi, > >Do you have any benchmark figures for MIPS 6000 cpu and the 6010 fpu? > >I was told that the new machine from DEC will be based on these chips, and >that Bull has already announced a machine with this chip. Any more information >on these new machines? Price information is also wanted. > >Thanks a lot for the information. I have the SPEC numbers for a MIPS RC6280 based on the R6000 CPU. Fortunately, I don't know more than epsilon about any other vendor's plans for using the ECL parts so I don't have to stifle myself when I say I don't know anything. Remember that these results are for one implementation of cache, system interconnect (in this case, a bus), and memory. These factors STRONGLY affect the performance you see. Here are SPEC numbers for BETA RC6280 systems at 60 MHz. These were published in the SPEC Spring Results Newsletter. The BETA unit is not peculiar, it has the same clock rate, cache size, and cache speed as the FCS unit so the performance should be essentially the same as an FCS unit. The BETA machine for this test has: CPU: MIPS R6000, Rev. 2.4, 60 MHz FPU: MIPS R6010, Rev. 2.1, 60 MHz Number of CPUs: 1 Cache Size: 16 KB primary data cache 64 KB primary instruction cache 512 KB secondary cache Memory: 32 MB Disk System: SMD O/S: RISC/os 4.50 Beta Compilers: CC & F77 Release 2.10 Beta Tuning Parameters: none in use Background load: none System State: multi-user, single user logged on Notes: All programs compiled "-O3" except 001 and 013 which used "-O2". All programs compiled with "-Olimit 2000 -mips2 -Wab -mips2rev210" For comparison, I have included the SPEC numbers from another MIPS box, the M/2000, a 25 MHz R3000-based system. This has 64KB instruction cache, 64KB data cache, 32 MB memory, compilers were 2.10 Beta. These figures taken Dec. 89. As a reminder, *'d ones are the integer ones. 001* 008* 013 015 020 022* 023* 030 042 047 SY gcc esp spic doduc nasa li eqn matrx fpp tom 44.5 43.7 37.7 38.3 39.6 44.9 35.6 52.4 52.2 36.8 1 19.1 18.2 12.1 17.6 18.4 23.8 18.3 13.3 20.4 17.7 2 SPEC integer SPEC Float SPECmark Systems 42.0 42.3 42.2 1 - BETA RC6280 @ 60MHz (R6000) 19.7 16.3 17.6 2 - MIPS M/2000 @ 25MHz (R3000) -- Charlie Price cprice@mips.mips.com (408) 720-1700 MIPS Computer Systems / 928 Arques Ave. / Sunnyvale, CA 94086