wendyt@june.cs.washington.edu (Wendy Thrash) (06/02/90)
In order to finish a paper by the end of this quarter (!), I need to get more detailed information on the Alliant FX/8 data cache than I currently have available. I'd appreciate mail from anyone who can tell me 1) Most important: How many bytes are in a cache line/block? 2) What's the difference between their "2-way interleaved" cache and a 2-way set associative cache? 3) When there are two cache modules on the system, does each service a separate four-CE clump (assuming 8 CE's)? What exactly do Alliant mean when they say that adding a second module produces a four-way interleaved cache? 4) Is it true that each cache module is 256K = 128K x 2? That's what my FX/8 Product Summary says, but Gallivan, Jalby, et. al. (1988 IJSCA) describe the FX/8 cache as 128K. Please note that this is not an attempt to get someone else to write the paper for me; I need more information about the cache to explain some anomalous (but pleasing) results I've produced.
fortuna@Alliant.COM (Mike Fortuna) (06/05/90)
In article <12104@june.cs.washington.edu> wendyt@june.cs.washington.edu (Wendy Thrash) writes: >In order to finish a paper by the end of this quarter (!), >I need to get more detailed information on the Alliant FX/8 >data cache than I currently have available. I'd appreciate >mail from anyone who can tell me >1) Most important: How many bytes are in a cache line/block? 8 bytes (64 bits) per line. Also known as a quad word. Each cache block contains 4 quad words. >2) What's the difference between their "2-way interleaved" > cache and a 2-way set associative cache? I'm not sure about 2-way set associative but two way interleaved means every other quad word resides in a different cache quadrant. Each cache module can be thought of as two independent caches (quadrants). Address bits 4 and 3 are used to select which quadrant as follows: Bit 4 Bit 3 Quadrant ----- ----- -------- 0 0 W 0 1 X 1 0 X 1 1 W >3) When there are two cache modules on the system, does each > service a separate four-CE clump (assuming 8 CE's)? No. Both modules service all the CEs. You can even run 8 CEs with one Cache Module. > What exactly do Alliant mean when they say that adding > a second module produces a four-way interleaved cache? Address bit 5 selects one of two cache modules. Address bits 4 and 3 select one of two quadrants per cache. Four quadrants imply four way interleaved. >4) Is it true that each cache module is 256K = 128K x 2? > That's what my FX/8 Product Summary says, but Gallivan, > Jalby, et. al. (1988 IJSCA) describe the FX/8 cache as 128K. Each original-design cache module contains two 32K quadrants (128K per system). Newer cache modules use larger SRAMs. I believe each cache quadrant is 128K. >Please note that this is not an attempt to get someone else to >write the paper for me; I need more information about the cache >to explain some anomalous (but pleasing) results I've produced. -- - Mike Fortuna VOICE: (508) 486-1240 Internet: fortuna@alliant.alliant.com SMAIL: 1 Monarch Drive UUCP: ...linus!alliant!fortuna Littleton, MA 01460