smv@necis.UUCP (Steve Valentine) (05/31/88)
In the 4/28/88 issue of Electronics on pg. 86, 2nd column there is a paragraph which reads as follows: "Features of the 88000 that suit it to use as a server include its register- scoreboarding capability, which makes it possible to for the system to switch from one task to another (called a context switch) in one clock cycle. To do this, the 88100 chip has duplicate sets of CPU registers used by different tasks running concurrently in the system. Switching from one task to another requires only a change in register sets." This seems to be a paraphrased statement by Thomas Mace of Convergent Tech. This is the only mention I have seen of the 88k having multiple register sets. Is this really true? If so, which registers are duplicated, and how many sets are there? Are CMMU registers duplicated as well? Do interrupts have to wait for special funtion units to complete the current instruction, or can they be taken concurrently? (Assuming the SFU is working on a many-clock instruction). It seems odd that this is the only reference to such an important feature. -- Steve Valentine - smv@necis.nec.com NEC Information Systems 1300 Massachusetts Ave., Boxborough, MA 01719 The whale, in fact, is not a fish. It is an insect, and it lives on bananas! - Peter Cook "Interesting Facts" Sketch
walter@garth.UUCP (Walter Bays) (06/01/88)
In article <631@necis.UUCP> smv@necis.UUCP (Steve Valentine) writes: >In the 4/28/88 issue of Electronics on pg. 86, 2nd column there is a paragraph >which reads as follows: > >"Features of the 88000 that suit it to use as a server include its register- >scoreboarding capability, which makes it possible to for the system to switch >from one task to another (called a context switch) in one clock cycle. To do >this, the 88100 chip has duplicate sets of CPU registers used by different tasks >running concurrently in the system. Switching from one task to another requires >only a change in register sets." > >This is the only mention I have seen of the 88k having multiple register sets. >Is this really true? According to the technical summary (document BR588/D; you can get one by calling Motorola) the 88100 has 32 general purpose registers, 1 wired to zero, 1 subroutine return pointer, 8 for subroutine parameters, 4 for temporaries, 12 for variables ("called procedure reserved"), 4 for use by the linker to synthesize 32 bit addresses, 1 frame pointer, and 1 stack pointer. Floating point instructions and supervisor mode share these same registers. Internal control registers are visible in supervisor mode. On page 77 of the same issue it's suggested (by another author) that scoreboarding means having a separate set of registers for each subroutine in order to facilitate task switching. (-: Does this imply TMS-9900 compatibility mode? :-) It would be interesting to learn whether a single fact gave rise to these strange interpretations. -- ------------------------------------------------------------------------------ I said it, not them. E-Mail route: ...!pyramid!garth!walter (415) 852-2384 USPS: Intergraph APD, 2400 Geng Road, Palo Alto, California 94303 ------------------------------------------------------------------------------
firth@sei.cmu.edu (Robert Firth) (06/02/88)
In article <631@necis.UUCP> smv@necis.UUCP (Steve Valentine) writes: >In the 4/28/88 issue of Electronics on pg. 86, 2nd column there is a paragraph >which reads as follows: > >"Features of the 88000 that suit it to use as a server include its register- >scoreboarding capability, which makes it possible to for the system to switch >from one task to another (called a context switch) in one clock cycle. To do >this, the 88100 chip has duplicate sets of CPU registers used by different >tasks running concurrently in the system. Switching from one task to >another requires only a change in register sets." (a) I don't see what register scoreboarding has to do with task context switching. Register scoreboarding allows the instruction immediately after a load to reference the load target, even with a load delay, by forcing a pause in the execution sequence. This is indeed a feature of the MC88000. (b) I've looked again, very carefully, through the MC88100 Technical Summary (Motorola ref BR588/D of April 1988), and can find no reference to duplicate sets of CPU registers. There is a set of virtual "shadow" registers whose main purpose is to allow precise hardware traps, but this again has nothing to do with task context switches. (c) As best I can tell, a complete context switch requires the save and restore of the equivalent of 64 32-bit registers; however, the description of the "Supervisor programming model" leaves unclear how much of this is necessary under what circumstances. A simple cooperative synchronization point seems to require about 15 regs to be saved and restored, if the Motorola codegeneration conventions are followed.
tom@nud.UUCP (Tom Armistead) (06/02/88)
In article <631@necis.UUCP> smv@necis.UUCP (Steve Valentine) writes: >This is the only mention I have seen of the 88k having multiple register sets. >Is this really true? If so, which registers are duplicated, and how many sets No, its not true. The only other "register set" that the 88100 has is the supervisor storage registers (cr17-cr20). These are merely read/write registers that can be used to quickly save away up to 4 of the general purpose registers (e.g. to guarantee low latency for real time interrupt handling). This is not register windowing which the article seemed to be eluding to. -- Just a few more bits in the stream. The Sneek
mslater@cup.portal.com (06/02/88)
> .. multiple register sets in 88K
Nothing in the Moto documentation suggests that this is true; from what
I know of the 88k, it does not have multiple register sets. I suspect
that the quote was botched. The same issue has a "quote" from me, which
bears no similarity to anything I ever said.
Michael Slater, Editor and Publisher, Microprocessor Report
550 California Ave., Suite 320, Palo Alto, CA 94306 (415) 494-2677