adamj@panews (02/21/91)
Does National Semiconductor's "Swordfish" microprocessor include an MMU? --Adam J. Richter adam@soda.berkeley.edu
gideon@tasu53.UUCP (Gideon Intrater) (02/21/91)
In article <1991Feb20.210752.19367@ibmpa.awdpa.ibm.com> adamj@kon-tiki.awdpa.ibm.com (Adam J. Richter) writes: > > Does National Semiconductor's "Swordfish" microprocessor include >an MMU? > > --Adam J. Richter > adam@soda.berkeley.edu No we don't have an MMU. Again, we target the processor for imaging embedded applications, where an MMU is usually not required. Our main design goal was to deliver as much performance at a low system cost. The Swordfish delivers more than 110,000 dhrystones/sec on a 25Mhz bus. Gideon Intrater Gideon Intrater gideon@nsc.nsc.com National Semiconductor, P.O.Box 3007, Herzlia B 46104, Israel Phone: +972-52-522255, Fax: +972-52-558322
mash@mips.COM (John Mashey) (02/26/91)
In article <5430@taux01.nsc.com> gideon@nsc.nsc.com (Gideon Intrater) writes: >No we don't have an MMU. Again, we target the processor for imaging embedded >applications, where an MMU is usually not required. Our main design goal >was to deliver as much performance at a low system cost. The Swordfish >delivers more than 110,000 dhrystones/sec on a 25Mhz bus. Although I haven't yet seen much detailed data, the swordfish at least looks like a reasonable implementation consistent with NSC's current strategy. However, I would observe that the number of dhrystones related to bus speed is kind of irrelevant for a processor with on-chip I-cache and write-back D-cache of any reasonable size.... -- -john mashey DISCLAIMER: <generic disclaimer, I speak for me only, etc> UUCP: mash@mips.com OR {ames,decwrl,prls,pyramid}!mips!mash DDD: 408-524-7015, 524-8253 or (main number) 408-720-1700 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086
mccalpin@perelandra.cms.udel.edu (John D. McCalpin) (02/26/91)
>>> On 25 Feb 91 21:21:13 GMT, mash@mips.COM (John Mashey) said: John> In article <5430@taux01.nsc.com> gideon@nsc.nsc.com (Gideon Intrater) writes: >The Swordfish delivers more than 110,000 dhrystones/sec on a 25Mhz bus. John> [...] I would observe that the number of dhrystones related to John> bus speed is kind of irrelevant for a processor with on-chip John> I-cache and write-back D-cache of any reasonable size.... Perhaps Gideon mentioned the bus speed since he wanted to say a 25 MHz cpu, but did not want to get into the details of what that meant, re possible internal clock-doubling, etc.... While we are on the topic, maybe John can tell us how is it that MIPS has managed to produce the CPU with the lowest ratio of "real" MIPS to dhrystone 1.1 MIPS among all the modern RISC processors? I don't know how the SPARC does, but I keep on seeing outrageous dhrystone 1.1 MIPS numbers for 88000 and RIOS machines -- the ratios are something like twice the ratios for the MIPS cpu's.... This low ratio for the MIPS processors seems to be some indication that the marketing department was not exercising adequate control over the design of the R2000/R3000. :-) -- John D. McCalpin mccalpin@perelandra.cms.udel.edu Assistant Professor mccalpin@brahms.udel.edu College of Marine Studies, U. Del. J.MCCALPIN/OMNET
gideon@taux01.nsc.com ( Gideon Intrater) (03/05/91)
In article <46175@mips.mips.COM> mash@mips.COM (John Mashey) writes: > >However, I would observe that the number of dhrystones related to >bus speed is kind of irrelevant for a processor with on-chip >I-cache and write-back D-cache of any reasonable size.... >-- >-john mashey DISCLAIMER: <generic disclaimer, I speak for me only, etc> >UUCP: mash@mips.com OR {ames,decwrl,prls,pyramid}!mips!mash The Swordfish has a write through data cache, so the bus configuration can change the performance (there are a lot of back to back writes in dhrystone). On a 25 Mhz bus with bus pipelining disabled the Swordfish delivers 110.1K dhrystones/sec. When the pipelining is enabled, it delivers 120.2K dhrystones/sec. I will post more benchmarks in the future. Note that we still do not have a SPEC suite for embedded controllers, so it is nearly impossible to compare the performance of different processors. -- Gideon Intrater gideon@nsc.nsc.com National Semiconductor, P.O.Box 3007, Herzlia B 46104, Israel Phone: +972-52-522255, Fax: +972-52-558322
mash@mips.com (John Mashey) (03/06/91)
In article <5486@taux01.nsc.com> gideon@taux01.nsc.com ( Gideon Intrater) writes: >In article <46175@mips.mips.COM> mash@mips.COM (John Mashey) writes: >> >>However, I would observe that the number of dhrystones related to >>bus speed is kind of irrelevant for a processor with on-chip >>I-cache and write-back D-cache of any reasonable size.... >The Swordfish has a write through data cache, so the bus configuration >can change the performance (there are a lot of back to back writes in >dhrystone). Mea culpa! I must have mis-read something somewhere, as I had it firmly in mind that the Swordfish had a write-back cache. sorry; there is indeed more correlation. Perhaps you can say a few words on the choice of write-thru versus write-back for this application? Also, can you describe the strcpy implementation used? >I will post more benchmarks in the future. Note that we still do not have >a SPEC suite for embedded controllers, so it is nearly impossible to compare >the performance of different processors. Yes. In fact, that would be a really good topic to discuss: for the embedded market, are there sensible benchmarks of the SPEC ilk? at least: public-domain or widely distributable (definitely NOT embedded ADA benchmarks of the "we have to shoot you after you read it" kind :-) reasonably portable written mostly in high-level languages run long enough to be meaningful measure things that practitioners can relate to -- -john mashey DISCLAIMER: <generic disclaimer, I speak for me only, etc> UUCP: mash@mips.com OR {ames,decwrl,prls,pyramid}!mips!mash DDD: 408-524-7015, 524-8253 or (main number) 408-720-1700 USPS: MIPS Computer Systems MS 1/05, 930 E. Arques, Sunnyvale, CA 94086