[comp.arch] Instruction caches and closures - why two caches???

mo@messy.bellcore.com (Michael O'Dell) (07/03/90)

The first is BANDWIDTH!!! Two caches gives you twice the number
of transactions per cycle.  This matters a lot on fast machines
with a lot of internal parallelism.

Secondly, the preferred (desired, first choice, optimum??) line
length for the i-cache might be very different depending
on how your machine handles prefetches, decoding, and branch prediction,
and the design details of the path to memory.  You never have to 
WRITE to the instruction cache or flush from it, only invalidate
(or wholesale invalidate).  Not needing a path back to memory
is a BIG DEAL in machines not built around minicomputer-style
busses.  

	-Mike