shri@ncst.ernet.in (H.Shrikumar) (12/26/90)
In article <PCG.90Dec22152204@odin.cs.aber.ac.uk> pcg@cs.aber.ac.uk (Piercarlo Grandi) writes: >success, to make ECL microprocessors. Urrah! for MIPS and FPS. I >remember that DG was developing an ECL 88K, it would be interesting to Any details, please ? this is interesting. >It would be even more interesting to read a simple summary to why it is >so much more difficult to make ECL microcomputers than CMOS ones. Is it >just the technology (power dissipation comes to mind immediately) or is >it that we are further down the learning curve with CMOS than ECL? The TOS on reasons-why-is-ECL-difficult is precisely why TTL (and TTL-mimicking CMOS) are easy to design. As you jack up speeds, the lengths of each pulse becomes comparable to the physical dimensions of the boards, and one need to have done a course on RF or Electro- magnetic fields and waves to understand what goes on there. In TTL you are blissfully unaware of all this (wonder why the scope and LA screens look different ? :-). Comp.arch is generally well aware of this issue. So when you bite ECL to break the TTL speed barrier you are already prepared to turn the trade-off-knob away from ease-of-design to willingness to deal with balanced signals, skew in their lengths, current mode logic levels, dielectric constant of the PCB epoxy, crosstalk and parasitic coupling, probably stopping just short of smith-charts :-) In short, you need to have got good grades in one more course (Fields&Waves) besides (digital electronics and computer organisation) to do an ECL board :-) At least this used to be the traditional ECL v/s TTL debate about a decade ago. I wonder of this has changed .... we now have BiCMOS, and TTL chips with ECL interconnects and GaAs ECL chips with TTL interconnect on the pins. So IMHO, its not just a ECL-TTL fence anymore but a family of fences between (A.logic+B.interconnect, A'.logic+B'.interconnet) technologies, where A,B,A',B' are elements of {ECL,TTL}. Thats a total of 12 fences ! ie. Is the "Viking" (*) internally ECL, with TTL interconnect ? (I presume so) or TTL with ECL interconnect (rationale: Pins are *the* bottleneck.) or ECL with ECL interconnect (real honest ECL all the way.) (TTL with TTL .... this it definitely is not, we're sure) Question: Isn't the ECL-TTL debate today clouded by these ? When you say "viking is a ECL sparc" which side of the fence is it ? More important, which fence ? -- shrikumar ( shri@ncst.in ) (*) Lets assume its been announced, (I didnt say by Sun, did I ? :-) PS: sorry if this is a repeat, rn died during my last attempt. Followups directed to comp.arch "Wishing all a happy new year and a great decade"