Daniel.Stodolsky@cs.cmu.edu (06/19/89)
When memory latency (I/O) dominates in an application, it seems like write-back caches should be a big win, particularly on single processor machines where you don't have to worry about cache coherency. So why don't we see more write-back D-caches? Daniel Stodolsky EDRC danner@edrc.cmu.edu
aglew@mcdurb.Urbana.Gould.COM (06/25/89)
>When memory latency (I/O) dominates in an application, it seems like >write-back caches should be a big win, particularly on single processor >machines where you don't have to worry about cache coherency. > >So why don't we see more write-back D-caches? > >Daniel Stodolsky >danner@edrc.cmu.edu They're out, and there are more coming. The MC88200 (the 88K's Cache and Memory Management Chip), for example, has copy-back, write-through, and cache inhibit for both 4K page and 512K blocks. The onset of busses like Futurebus will make write-back caches more available - at the moment write-back usually has to be implemented with a private, proprietary bus (ie. the standard busses don't support write-back very well). As an aside, however, may I note that you may have confused write-back with write buffering. Even on a write-through cache you do not need to wait for memory latency, if the write can be buffered and the processor can continue execution immediately. Write back makes the buffer as big as the cache, but is usually not coupled with trickle back.