[comp.arch] HP Precision Architecture

reid@sask.UUCP (I am NOT your Sweet Baboo) (03/17/87)

In article <1308@ucbcad.berkeley.edu>, faustus@ucbcad.berkeley.edu (Wayne A. Christopher) writes:
> I just read somewhere that the new HP Precision Architecture supports "up
> to 64-bit virtual addresses".  It seems to have a 32-bit internal datapath,
> however.  Can anybody explain what the 64-bit addresses are?
> 	Wayne

Like I said in the Summary, they allow (in the long run...) a 32-bit segment
number, with 32 bits address space in each segment.  They gave a
presentation here a little while ago and told us all about it.

I think they said that they didn't use the segment register for much yet,
since they didn't really need it.

Does this mean we're going have "small memory model" and "large memory
model" compilers? :-)

 - irving "just in case 4 Gbytes isn't enough" reid -
-- 
reid@sask.uucp                          {alberta, ihnp4, utcsri}!sask!reid

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