raymond@pioneer.arc.nasa.gov.arpa (Eric A. Raymond) (10/22/88)
DIn article <19191@apple.Apple.COM> malcolm@Apple.COM (Malcolm Slaney) writes: >>must be backward compatible. Even so, there are no new CISC designs >>being done, that I know of. > >Ummm, I think Symbolics and TI would probably argue with this statement. >Both companies have recently introduced Lisp machines on a chip....and nobody >will ever call a conventional Lisp machine architecture a RISC. Hmmm. Have you ever looked at a Lisp Machine? Sure its not a RISC because its microcoded, but there are some similarities. Things like barrel shifters (for extracting tags) come to mind. The instruction set is not all that complex. Sure it doesn't have lots of registers, but its paradigm is a stack machine (you might consider its on-chip stack to be registers). Anyway, nobody ever said that RISC meant lots of registers. This is where TI ends (I believe) and Symbolics goes on (the tags that is). At least that's where the CADR (LMI and TI didn't really vary from this design) left off. The neat trick which the Symbolics introduced in the 3600 (and now in Ivory) was to allow parallel execution of instructions, type checking, GC related checks ,etc. If one of these traps suceeded, then a different instruction would be called. These extra checks caused no overhead in the base case. (i.e. Assume operands to add are integers. If it turns out that they are not, then execute the floating point add. The beauty is that if they were integers, then you already have your answer and the type check was free.) Does this sound familiar? They also did things like go to larger word sizes (36 & 40) and CDR coding (I don't think CADR had this - might be wrong). Please flame on me and set me straight if I'm wrong. Note that both RISC and LISPM-chip (read stack machine with tag bits) are vague terms. Also note that in every respect other than development environments (and their not really that far behind anymore) RISC machine LISP >= LISPM. By the way, Envos, a Xerox spinoff, sells the Xerox LISP environment for SUN 4's which is 2x faster than the 1108's were. Not that the d-machines were nkown for speed .... Xerox does not sell machines anymore. Name: Eric A. Raymond ARPA: raymond@pioneer.arc.nasa.gov SLOW: NASA Ames Research Center, MS 244-17, Moffett Field, CA 94035 Nothing left to do but :-) :-) :-)
pardo@june.cs.washington.edu (David Keppel) (10/22/88)
raymond@pioneer.arc.nasa.gov.UUCP (Eric A. Raymond) writes: >malcolm@Apple.COM (Malcolm Slaney) writes: >>[ somebody? ] >>>must be backward compatible. Even so, there are no new CISC designs >>>being done, that I know of. Oh, heck, there's some (relatively) new supercomputer being produced by some subsidiary of CDC (I think?) that was written up in "digital review" a month or so ago. It is described as "VCISC" -- Very CISC. It includes as part of its basic instructin set a whole smear of vector opcodes, which can operate on chunks of memory up to 1 page; several page sizes are supported, I believe that the largest is 64K 64-bit words = 1/2 Mbyte. Physical memories of up to about 2Gbytes or 2Gwords (I forget) are availabale, liquid Nitrogen is optional. Next model is due in December or so and should bench the Livermore Loops with the best of the Crays. Also, while CISC is out of vogue in new industry designs at the moment, there are plenty of Universities building microcoded processors (read "CISC"?). ;-D on ( Just don't page fault very often.... ) Pardo -- pardo@cs.washington.edu {rutgers,cornell,ucsd,ubc-cs,tektronix}!uw-beaver!june!pardo
bcase@cup.portal.com (Brian bcase Case) (10/23/88)
>Anyway, nobody ever said that RISC meant lots of registers. Maybe nobody ever said it, but I would be willing to go out on limb and say it if someone asked. :-) >Please flame on me and set me straight if I'm wrong. Do we now need a group "alt.masochists"? :-) >Not that the d-machines were nkown for speed .... They had plenty of speed (Dorado had (I think) an ECL implementation, a 45 ns cycle time, and sophistiated caching long before it came down to that class of machine in the real world). They just hid the speed below a few layers of microcode. :-)
pf@csc.ti.com (Paul Fuqua) (10/23/88)
Date: Friday, October 21, 1988 8:26pm (CDT)
From: raymond at pioneer.arc.nasa.gov.arpa (Eric A. Raymond)
Subject: LISPMs not RISC? - Re: CISCy RISC? RISCy CISC?
Newsgroups: comp.arch
This is where TI ends (I believe) and Symbolics goes on (the tags that is).
At least that's where the CADR (LMI and TI didn't really vary from this
design) left off.
Not true. The Explorer 1 (can you say retronym?) has some ability to do
type checks in parallel, and the Explorer 2 has even more. My first
assignment back in 1984 was to update the arithmetic microcode to use
it. LMI may not have varied much (I really don't know), but TI did a
little with the 1 and quite a bit with the 2.
They also did things like go to larger word
sizes (36 & 40) and CDR coding (I don't think CADR had this - might be wrong).
CDR-coding did exist in the CADR -- it was a microcode phenomenon, not a
hardware one.
Note that both
RISC and LISPM-chip (read stack machine with tag bits) are vague terms.
One CADR paper I have makes the careful distinction between the CADR
machine, which is a microprogrammable 32-bit general-purpose processor
with some fancy features, and the Lisp machine, which is the engine plus
the microcode to run Lisp. The distinction has blurred in later
designs, what with the Ivory containing Lisp microcode in ROM and the TI
chip having some hardware recognition of macroinstructions.
pf
Paul Fuqua
Texas Instruments Computer Science Center, Dallas, Texas
CSNet: pf@csc.ti.com (ARPA too, sometimes)
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