jones@pyrite.cs.uiowa.edu (Douglas W. Jones,201H MLH,3193350740,3193382879) (03/29/91)
The claim that an architecture is or is not a Von Neumann architecture is very frequently made in a misleading way. Some people will use it as a perjorative term in reference to "The Von Neumann" bottleneck between processor and memory, others refer to the Von Neumann model of memory addressing (all of memory is one big array). Back in 1973, I remember a final exam question at Carnegie-Mellon University; I think it was in Sam Fuller's class, but I'm not sure. The question was: Name six features common on modern machines which were not present in the architectures proposed by Von Neumann. (The number six might have been something else, I forget). I think the point of this question was, at least in part, to get people to think twice before characterizing an architecture as non-Von Neumann by pointing out that essentially all modern architectures contain features which are quite correctly described as such. The next page of this note contains a list of popular non-Von Neumann features in modern architectures: 1) Indexed addressing. 2) Indirect addressing. 3) Multiple accumulators. 4) Peripheral processors, I/O channels, DMA, or any similar feature. 5) Floating point. 6) Fractional or multiple word operands. 7) Procedure call instructions. 8) Stacks, whether used for call and return or anything else. 9) Any distinction between virtual and physical memory addresses. It's worth noting that Von Neumann is supposed to have objected to the introduction of floating point with the line "Any programmer worth his salt should be able to keep the decimal point in his head." It's also worth remembering that Von Neumann may have anticipated the idea of fractional word operands by packing multiple instructions per word. Doug Jones jones@cs.uiowa.edu
cgy@cs.brown.edu (Curtis Yarvin) (03/29/91)
In article <5104@ns-mx.uiowa.edu> jones@pyrite.cs.uiowa.edu (Douglas W. Jones,201H MLH,3193350740,3193382879) writes: >The claim that an architecture is or is not a Von Neumann architecture >is very frequently made in a misleading way. ... >pointing out that essentially all modern architectures contain features >which are quite correctly described as such. >The next page of this note contains a list of popular non-Von Neumann >features in modern architectures: >1) Indexed addressing. >2) Indirect addressing. >3) Multiple accumulators. [et cetera] The next line of this note contains a list of popular non-Von Neumann features in modern architectures: 1) Transistors. Mr. Jones and the original poster (Firth?) are talking about two quite different things. Mr. Jones mentions a few _additions_ to the Von Neumann concept of a computer. These are, unsurprisingly, numerous. Computer architecture has made a few minor advances in the past 40 years. The original poster, however, was vilifying features of modern machinery which represent _reductions_ of the capability of Von Neumann machines. For example, an ideal Von Neumann computer has an individual data/instruction space; it can execute data or modify instructions. Most modern processors, however, separate I- and D- caches, often resulting in some loss of the ability to execute self-modifying code. It is, however, possible to get into fierce but meaningless arguments over whether segments represent such a reduction. Curtis "I tried living in the real world Instead of a shell But I was bored before I even began." - The Smiths
mark@hubcap.clemson.edu (Mark Smotherman) (03/29/91)
From article <5104@ns-mx.uiowa.edu>, by jones@pyrite.cs.uiowa.edu (Douglas W. Jones,201H MLH,3193350740,3193382879): > list of popular non-Von Neumann features in modern architectures: > 1) Indexed addressing. > 2) Indirect addressing. > 3) Multiple accumulators. > 4) Peripheral processors, I/O channels, DMA, or any similar feature. > 5) Floating point. > 6) Fractional or multiple word operands. > 7) Procedure call instructions. > 8) Stacks, whether used for call and return or anything else. > 9) Any distinction between virtual and physical memory addresses. An evaluation of the IAS machine that I give to my architecture class each semester: von Neumann machine characteristics random-access, one-dimensional memory stored program, no distinction between instructions and data binary, parallel by word, two's complement instruction fetch/execute cycle, branch by explicit change of PC three-register arithmetic (ACC, MQ, MBR) in his classic report, von Neumann foresaw the use of floating point (IBM 704, 1954) [he rejected it as wasteful] indexing (Univ. of Manchester, 1949) multiple precision arithmetic hexadecimal notation policing of unassigned opcodes single-stepping for debugging pipelining (IBM Stretch, 1961) CPU-bound vs. I/O-bound behavior archival storage later innovations buffered I/O (Univac I, 1951) subroutine call instructions (Univac 1103A, 1954) [possibly earlier?] interrupts (Univac 1103A, 1954) interrupts for I/O (NBS DYSEAC, 1954) DMA (IBM SAGE, 1955) duplex processors (IBM SAGE, 1955) indirect addressing (IBM 704, 1956) general purpose register set (Ferrante Pegasus, 1956) I/O channels (IBM 709, 1957) virtual memory (paging, Univ. of Manchester Atlas, 1959) segmentation (B5000, 1960) symmetric multiprocessor system (Burroughs D-825, 1960) computer family (IBM S/360, 1964) out-of-order execution (CDC 6600, 1964) An evaluation of the IAS machine (ca. 1946) I. programming language support A. one integer data type (can be viewed as scaled fraction) 1. 40 bits, binary, two's complement 2. range is -2^39 to (2^39)-1 B. no character data type C. control structures 1. procedure call by instruction modification (i.e. insert return address directly into return jump) 2. single type of conditional jump 3. for loop implemented by counting down from N-1 to 0 D. 12-bit addressability; no addressing modes 1. scanning an array by explicit address update and instruction modification (i.e. insert element address into accessing inst.) 2. traversing a linked list by instruction modification II. operating system support A. limited I/O 1. I/O device interconnection through CPU 2. no CPU-I/O overlap 3. no I/O interrupt B. no protection 1. one mode of execution 2. unprotected memory 3. no protection violation interrupts An evaluation of the IBM 7094 (1962) I. programming language support A. integer data type 1. 36 bits, binary, signed magnitude 2. range is -(2^35)+1 to (2^35)-1 B. 6-bit character data type, packed six to a word C. single-precision floating point data type 1. signed magnitude mantissa with bias notation exponent 2. precision given by 27-bit fractional mantissa 3. range given by 8-bit bias-128 exponent = 2^-128 to 2^-127 D. double-precision floating point data type E. 36-bit logical vector data type F. control structures 1. procedure call by TSX instruction, return address in index register 2. numerous conditional jumps and skips 3. for loop implemented with several fast loop closing instructions G. 15-bit addressability; direct, indexed, and indirect addressing modes 1. scanning an array by use of (seven) index registers 2. traversing a linked list by indirect addressing II. operating system support A. sophisticated I/O 1. I/O device interconnection through memory switch 2. CPU-I/O overlap possible using concurrency of I/O channels (separate processors with their own PCs and programs in shared main memory, operates asynchronously with CPU, started by a CPU instructions, and synchronizes upon end or error via interrupt) 3. I/O interrupt B. little protection 1. two modes of execution, normal and trapping after each jump (used for program tracing) 2. unprotected memory 3. some protection violation checks cause machine halt Assignments can involve doing a similar evaluation of the DEC VAX-11/780 (1978 -- note 16 years difference between each machine, and what a difference it makes!) and also what a 1994 architecture will look like. -- Mark Smotherman, Comp. Sci. Dept., Clemson University, Clemson, SC 29634 INTERNET: mark@hubcap.clemson.edu UUCP: gatech!hubcap!mark