pavern@uk.ac.man.cs (Nigel Paver (IW ra)) (01/08/91)
I am interested in finding out information about:
Asynchronous Microprocessors
Asynchronous Design Techniques (related to Microprocessors)
Can anybody suggest any suitable references, or research groups working
in this area. I believe there is at group a Caltech (Alain Martin et. al),
but I do not have an email address for them.
Please Email replies to me and I will summarize to the net if there is
sufficient interest.
Thanks in Advance
Nigel
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Nigel Paver.
AMULET Group, Room 407 IT Building, Department of Computer Science,
University of Manchester, Oxford Road, Manchester, M13 9PL, UK.
Janet: pavern@uk.ac.man.cs Tel: +44-61-275-6292
UUCP: ...!uunet!mcsun!ukc!man.cs!pavern Fax: +44-61-275-6280
Inet: pavern%cs.man.ac.uk@nsfnet-relay.ac.uk Int: 6292
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Nigel Paver.
EDS Group, Room 407 IT Building, Department of Computer Science,
University of Manchester, Oxford Road, Manchester, M13 9PL, UK.
Janet: pavern@uk.ac.man.cs Tel: +44-61-275-6292
UUCP: ...!uunet!mcsun!ukc!man.cs!pavern Fax: +44-61-275-6280
Inet: pavern%cs.man.ac.uk@nsfnet-relay.ac.uk Int: 6292
-----------------------------------------------------------------------------mark@mips.COM (Mark G. Johnson) (01/08/91)
> >Can anybody suggest any suitable references, or research groups >working in this area > Abbreviated Abstract: [emphasis mine] "Self-timing *introducing no delay overhead* controls a 7mm2 iterating ring for mantissa computation of floating-point division. The datapath has embedded completion encoding *and no latches*. Quotients and done indication appear in 45 to 160ns, depending on data operands. Implementation is in 1.2 um CMOS technology." Parenthetical Note: [mine] Present generation RISCs use 0.8 um CMOS technology (considerably better than 1.2 um) and achieve divide times of 300 - 700ns [Hennessey and Patterson page A-53]. They include, of course, the additional overhead of exponent calculations. Citation: Ted Williams and Mark Horowitz, "A Zero-Overhead Self Timed 160ns 54bit CMOS Divider," paper 5.5, IEEE International Solid State Circuits Conference (ISSCC), February 14, 1991, San Francisco. -- -- Mark Johnson MIPS Computer Systems, 930 E. Arques M/S 2-02, Sunnyvale, CA 94086 (408) 524-8308 mark@mips.com {or ...!decwrl!mips!mark}
adm@otter.hpl.hp.com (Alan Marshall) (01/09/91)
/ otter:comp.arch / pavern@uk.ac.man.cs (Nigel Paver (IW ra)) / 4:36 pm Jan 7, 1991 /
I am interested in finding out information about:
Asynchronous Microprocessors
Asynchronous Design Techniques (related to Microprocessors)
Can anybody suggest any suitable references, or research groups working
in this area. I believe there is at group a Caltech (Alain Martin et. al),
but I do not have an email address for them.
Please Email replies to me and I will summarize to the net if there is
sufficient interest.
Thanks in Advance
Nigel
-----------------------------------------------------------------------------
Nigel Paver.
AMULET Group, Room 407 IT Building, Department of Computer Science,
University of Manchester, Oxford Road, Manchester, M13 9PL, UK.
Janet: pavern@uk.ac.man.cs Tel: +44-61-275-6292
UUCP: ...!uunet!mcsun!ukc!man.cs!pavern Fax: +44-61-275-6280
Inet: pavern%cs.man.ac.uk@nsfnet-relay.ac.uk Int: 6292
-----------------------------------------------------------------------------
--
-----------------------------------------------------------------------------
Nigel Paver.
EDS Group, Room 407 IT Building, Department of Computer Science,
University of Manchester, Oxford Road, Manchester, M13 9PL, UK.
Janet: pavern@uk.ac.man.cs Tel: +44-61-275-6292
UUCP: ...!uunet!mcsun!ukc!man.cs!pavern Fax: +44-61-275-6280
Inet: pavern%cs.man.ac.uk@nsfnet-relay.ac.uk Int: 6292
-----------------------------------------------------------------------------
----------ccplumb@rose.uwaterloo.ca (Colin Plumb) (01/26/91)
One alternate variation on "self-clocking" has also been used. Bipolar Integrated Technology, makers of all kinds of fast ECL goodies did a floating point ALU that ran off an internally-generated 500 MHz clock. (I believe it was one generation before their current 10 ns pipe/20 ns latency hot boxes). The hard part, I was told in a bull session with one of their engineers, was getting the oscillator speed to scale with the rest of the chip, because you can't speed-grade the things. Either they work, or they don't. It was, I was told, a nifty idea, and they got it working, but never again. -- -Colin