baum@Apple.COM (Allen J. Baum) (11/22/88)
[] >In article <11123@reed.UUCP> mdr@reed.UUCP (Mike Rutenberg) writes: >In article <23585@amdcad.AMD.COM> tim@crackle.amd.com (Tim Olson) writes: >>Most RISCs have parallel load/store, however, "scoreboarding" (i.e. the >>existance of an "in-use" bit per register) is not the only way to >>guarantee correct operation. The 29000, for example, associates an >>8-bit register number with the load unit, which is compared to the >>operand fields of subsequent instructions. If there is a match, then >>the pipeline is stalled until the load is complete. This is much >>cheaper (8-bit register + 2 8-bit comparitors) than 192 bits worth of >>scoreboard. In addition, the comparison registers are required to >>perform forwarding, anyway. > Note that unlike what the above implies, you can have more than one tag, and keep more than one outstanding request going. One tag may cost as much as 8 (in the above example) scoreboard bits, so there is a crossover point (although the analysis of that is not very simple- detailed design is necessary). One of the IBM RISC patents covers the multi-tag concept (#4,630,195). On the other hand, how many outstanding requests will you have (mileage may vary for VLIWs). Summary: 1 bit/reg. lets you have as many outstanding requests as you have regs. tagging lets you have as many outstanding requests as you have tags (besides which, you often need tags for forwarding anyway) -- baum@apple.com (408)974-3385 {decwrl,hplabs}!amdahl!apple!baum