lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay) (10/05/89)
The October IEEE Spectrum has an interesting article called "Microprocessors circa 2000". It seems to be a semiofficial statement from Intel, and it's optimistic about the coming decade. Specifically, the hot chip they expect (the "Micro 2000") is: 250 MHz 0.1 micron minimum device geometries one square inch 3.3 or 2.5 V power supply "innovative refrigeration techniques may be needed" 50-100 million transistors, budgeted as follows: 4 CPUs @ 4M each 2 vector units @ 4M each graphics unit, 4M bus interface, 2M self test, 3M shared cache, 2MB Each vector unit delivers 4 results/clock. Each CPU does 3 instructions/clock. They made no comment about logic families, except that the word "silicon" did escape their lips. ---------------------------- It is rumored that multiple-CPU chips really are in the works, and for 1991, not for 2000. (No, I don't mean university projects, or published designs such as TRAC.) If they are going to happen, what would people like to see? How should the units communicate? What about internal vs external interrupts; MMU[s]; local caches; semaphores; hardware forks? Any shared-register fans out there? -- Don D.C.Lindsay Carnegie Mellon Computer Science
hankd@pur-ee.UUCP (Hank Dietz) (10/05/89)
In article <6415@pt.cs.cmu.edu> lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay) writes: >It is rumored that multiple-CPU chips really are in the works, and >for 1991, not for 2000. (No, I don't mean university projects, or >published designs such as TRAC.) > >If they are going to happen, what would people like to see? How >should the units communicate? What about internal vs external >interrupts; MMU[s]; local caches; semaphores; hardware forks? >Any shared-register fans out there? As an academic optimizing/parallelizing compiler researcher, it has long been apparent to me that the way to build big machines is as MIMD machines with physically-distributed memory (accessed by a shared address space) such that each node in the MIMD is actually a single-chip VLIW or other fine-grain processor arrangement. The first such design I proposed was presented at the Second SIAM Conference on Parallel Processing for Scientific Computing, November 20, 1985: Henry G. Dietz and A. David Klappholz, "RISC CPU Design for MIMDs." The current design is quite different -- the CARP (Compiler-oriented Architecture Research at Purdue) machine. We haven't got any details out in papers yet, but we have a fairly complete paper design (also a simulator, assembler, and compilers working for at least parts of the machine). As soon as we finish THE CARP machine technical report, I'll post the reference so that you can all get copies... but here is a quick summary: Full machine: A MIMD with ~64 nodes Node: One Chip (min. of 100K trans. equiv.) containing at least: 4 32-bit Integer Processors (IPs), each with: 18 instructions, 8 bits explicit control 16 data CRegs (Cache-REGisters) 16 4-word instruction CRegs Some CRegs shared with other IPs Separate global/local memory access busses No interrupts allowed (delayed for free Node or IP) "Smart cache" network interface (based on RFM+) Barrier sync. processor (Allows asynchronous execution, but also lets compiler use static VLIW-like scheduling) 1 64-bit Float Processor (FP), with: ~2 instructions (mul & recip) General layout as IPs... Memory mgmt: Virtual memory paging (pages are local to node) Some explicit control over page handling I/O is memory-mapped Network: Topology... probably single-stage (recirc.) net, but not certain Switches... within nodes... explicit control of caching MIMD inter-node sync. as semaphores in network -hankd@ecn.purdue.edu
henry@utzoo.uucp (Henry Spencer) (10/06/89)
In article <6415@pt.cs.cmu.edu> lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay) writes: >"Microprocessors circa 2000"... seems to be a semiofficial statement >from Intel... >Specifically, the hot chip they expect (the "Micro 2000") is: ... > 4 CPUs @ 4M each Let me guess... One 286, one 386, one 80960, and one 860. :-) :-) :-) (Hey, it eliminates the compatibility problems...) -- Nature is blind; Man is merely | Henry Spencer at U of Toronto Zoology shortsighted (and improving). | uunet!attcan!utzoo!henry henry@zoo.toronto.edu
mangler@cit-vax.Caltech.Edu (Don Speck) (10/15/89)
In article <6415@pt.cs.cmu.edu>, lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay) writes: > Specifically, the hot chip they expect (the "Micro 2000") is: > 250 MHz > 0.1 micron minimum device geometries > one square inch > 3.3 or 2.5 V power supply > "innovative refrigeration techniques may be needed" Power consumption depends on the product of: clock rate (6.25 times the i860) active silicon area (4 times the i860) capacitance per unit area (dielectrics 4 times as thin as i860) power supply voltage (1/2 of i860) duty factor of signals (probably similar amount of pipelining) This predicts that the "Micro 2000" will draw 50 times the amperage of the i860. Hot chip indeed. To bring this much current 1 cm into the chip on 1-cm wide aluminum with a 0.2V drop, the aluminum will have to be 5 microns thick (thickness 50 times the width of the narrowest underlying wires).