lamaster@ames.arc.nasa.gov (Hugh LaMaster) (11/17/88)
In article <543@acorn.UUCP> RWilson@acorn.co.uk writes: >Acorn and built using VLSI Technology Inc's (VTI) 3 micron double level metal >CMOS process using full custom techniques; samples, working first time, were >respectively. The ARM comprises 24,000 transistors (circa 8,000 gates). Every > > > I know this must be obvious to many hardware types out there, but, is this ratio of transistors/gates typical for CMOS? -- Hugh LaMaster, m/s 233-9, UUCP ames!lamaster NASA Ames Research Center ARPA lamaster@ames.arc.nasa.gov Moffett Field, CA 94035 Phone: (415)694-6117
seeger@beach.cis.ufl.edu (F. L. Charles Seeger III) (11/22/88)
Well, I haven't seen a posted answer to this: In article <18267@ames.arc.nasa.gov> lamaster@ames.arc.nasa.gov.UUCP (Hugh LaMaster) writes: |In article <543@acorn.UUCP> RWilson@acorn.co.uk writes: |>respectively. The ARM comprises 24,000 transistors (circa 8,000 gates). | |I know this must be obvious to many hardware types out there, but, is this |ratio of transistors/gates typical for CMOS? I can't speak much about real world practice, but can give a brief background, since no one else has answered publicly. Of course, counting these things is a bit open to interpretation, e.g. what is a typical gate? how to count a PLA or memory cell? etc. I prefer to count transistors and IO pads, realizing, of course, that yield and die area are the most important economic measures, for a given process. A fully static CMOS gate will typically have two transistors per input signal. This is why CMOS transistors are sometimes counted in pairs (one n-type and one p-type). If we assume as our reference gates with two inputs, then we should expect 4 transistors/gate. However, CMOS is very rich in the variety of logic circuit techniques that can be used, most of which reduce the transistor count but may decrease speed, increase circuit complexity and create debugging problems (i.e. it tends to be easier to debug fully static designs). Good simulation tools make these trade-offs more predictable. For example, these logic structures include pseudo-nmos, dynamic, clocked, domino, pass transistors and cascade voltage switches. The use of dynamic logic is signified by a *minimum* clock rate for a part, which is common for microprocessors. Weste and Eshraghian's book, _Principles_of_CMOS_VLSI_Design_A_Systems_Perspective_ ('85), is a good introduction to these logic families. I hope this wasn't too far off from the answer that you were seeking. Chuck -- Charles Seeger 216 Larsen Hall Electrical Engineering University of Florida seeger@iec.ufl.edu Gainesville, FL 32611
lamaster@ames.arc.nasa.gov (Hugh LaMaster) (11/23/88)
In article <19323@uflorida.cis.ufl.EDU> seeger@beach.cis.ufl.edu (F. L. Charles Seeger III) writes: >I can't speak much about real world practice, but can give a brief >background, since no one else has answered publicly. Of course, counting >these things is a bit open to interpretation, e.g. what is a typical >gate? how to count a PLA or memory cell? etc. I prefer to count Well, what I am really driving at is "4 input nand gate equivalents". (Or 2 input nand gate equivalents, if that makes more sense...) The reason is just that there is no convenient way to judge CPU complexity by "number of transistors" without knowing a lot about the technology. I am looking for a ROUGH estimate of complexity independent of the number of transistors. I may be wrong, but may guess is that there is some easy and CONSISTENT way to measure CPU complexity which is ROUGHLY correct (within a factor of two). Am I the only person out there wondering how much logic can be packed onto one of those new GaAs micros, and would like to compare that to a uVAX or MIPS chip? Since this isn't going to be of use to marketeers, a simple measure which is USUALLY only slightly misleading would be of use. -- Hugh LaMaster, m/s 233-9, UUCP ames!lamaster NASA Ames Research Center ARPA lamaster@ames.arc.nasa.gov Moffett Field, CA 94035 Phone: (415)694-6117
seeger@beach.cis.ufl.edu (F. L. Charles Seeger III) (11/23/88)
In article <19323@uflorida.cis.ufl.EDU> I wrote: |>I can't speak much about real world practice, but can give a brief |>background, since no one else has answered publicly. Of course, counting |>these things is a bit open to interpretation, e.g. what is a typical |>gate? how to count a PLA or memory cell? etc. I prefer to count In article <18574@ames.arc.nasa.gov> lamaster@ames.arc.nasa.gov.UUCP (Hugh LaMaster) writes: |Well, what I am really driving at is "4 input nand gate equivalents". |(Or 2 input nand gate equivalents, if that makes more sense...) It doesn't necessarily make any more sense, but "equivalent 2-input nand gates" has been used, at least by some ASIC vendors. |The reason is just that there is no convenient way to judge CPU |complexity by "number of transistors" without knowing a lot about the |technology. I am looking for a ROUGH estimate of complexity independent |of the number of transistors. | |I may be wrong, but may guess is that there is some easy and CONSISTENT |way to measure CPU complexity which is ROUGHLY correct (within a factor |of two). Am I the only person out there wondering how much logic can be |packed onto one of those new GaAs micros, and would like to compare that |to a uVAX or MIPS chip? Modulo 2, transistor count may be as good as anything, especially if you account for the technology. It is certainly easier to make this count than that of gates, though we should restrict ourselves to counting logic gates/transistors to measure complexity, i.e. not drive inverters/ transistors. We might want to count memory/register cells separately. If roughness is OK, the number of transistors in an N-input gate rarely fall outside the (1.25-2.0)*N range. The only other way to make this measurement, that springs to my feeble mind, is to do some sort of analysis of the logic equations and state machines (automata, for you CS guys) that are implemented. I won't even think about trying to measure the dynamic complexity of the chip, though this is probably the most important. However, this sort of approach is open to the same problems as regular benchmarking. It certainly wouldn't be "easy and CONSISTENT." Then again, I only vaguely have an idea as to what complexity is. If I don't know how to measure it ... |Since this isn't going to be of use to |marketeers, a simple measure which is USUALLY only slightly misleading |would be of use. If many people start quoting it, the marketeers will, too. Transistor counts used to be mentioned as new microprocessors were introduced. It's probably progress to quote MIPS/dhrystones per buck rather than the gate count (i.e. the dynamic utility vs. static existence). Either way, there's a lot more to life than can be stuffed into a checksum. Regards -- Charles Seeger 216 Larsen Hall Electrical Engineering University of Florida seeger@iec.ufl.edu Gainesville, FL 32611
aglew@mcdurb.Urbana.Gould.COM (11/26/88)
|The reason is just that there is no convenient way to judge CPU |complexity by "number of transistors" without knowing a lot about the |technology. I am looking for a ROUGH estimate of complexity independent |of the number of transistors. | |I may be wrong, but may guess is that there is some easy and CONSISTENT |way to measure CPU complexity which is ROUGHLY correct (within a factor |of two). Am I the only person out there wondering how much logic can be |packed onto one of those new GaAs micros, and would like to compare that |to a uVAX or MIPS chip? One of the trade mags (I think it's VLSI Design) is flogging a set of "benchmark circuits". The idea is that you take, say, MSI components, and then see how many devices and how much area it takes to implement that component in a given technology. The purpose is mainly to compare gate arrays and not-quite-full-custom logic families -- in gate arrays especially, the way in which the manufacturer lays the array out can make a great difference in how costly it is to implement a given function. It may be possible to customize these benchmarks in order to compare full-custom technologies. Andy "Krazy" Glew aglew@urbana.mcd.mot.com uunet!uiucdcs!mcdurb!aglew Motorola Microcomputer Division, Champaign-Urbana Design Center 1101 E. University, Urbana, Illinois 61801, USA. My opinions are my own, and are not the opinions of my employer, or any other organisation. I indicate my company only so that the reader may account for any possible bias I may have towards our products.
aglew@mcdurb.Urbana.Gould.COM (11/26/88)
>If many people start quoting it, the marketeers will, too. Transistor >counts used to be mentioned as new microprocessors were introduced. It's >probably progress to quote MIPS/dhrystones per buck rather than the >gate count (i.e. the dynamic utility vs. static existence). Either way, >there's a lot more to life than can be stuffed into a checksum. >-- > Charles Seeger Now there's a thought. Maybe we should Go:delize a complete description of each system, and let the marketeers play with that.