brandis@inf.ethz.ch (Marc Brandis) (02/07/91)
In article <2896@charon.cwi.nl> dik@cwi.nl (Dik T. Winter) writes: >I believe some versions of the i960 can issue three instructions at the same >time (but I understand the next cycle they can issue at most one instruction). >The RS6000 can issue three *different* kinds of instructions at the same time >(where different is different from the different of the i860). This is not completely correct. The S/6000 can issue four different instructions every cycle, although one comes from a rarely used class (condition code operations). To me, it is still unclear what these instructions should be really useful for. The i960CA can theoretically issue three instructions every cycle, and it is not true that in the following cycle only one instruction can be issued. They have also to be of different classes: one branch, one arithmetic or logic, one memory access. Some time ago I collected information about the i960CA, and the common experience with it as well as the impression of computer architects was that the i960CA is not faster than traditional RISCs (e.g. like the Am29k or the SPARC) at the same clock speed and with similar memory subsystems. The reasons were mainly the slow memory access times and the high costs of conditional branches. However, you should not forget that the i960CA was designed as a processor for embedded applications, so performance was not the most important design issue. Marc-Michael Brandis Computer Systems Laboratory, ETH-Zentrum (Swiss Federal Institute of Technology) CH-8092 Zurich, Switzerland email: brandis@inf.ethz.ch